公开(公告)号：EP0139366A1

公开(公告)日：1985-05-02

申请号：EP84305337.2

申请日：1984-08-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Harada, Nozomu Patent Division Toshiba Corp. ,  Komatsubara, Yoshiaki Patent Division

IPC分类号： H01L21/90 ,  H01L27/14

CPC分类号： H01L27/14893 ,  H01L27/14806 ,  Y10S148/075 ,  Y10S148/172

摘要： When a "two-level" solid state image pickup device is manufactured, part of a first metallic electrode (28a) electrically connected to a signal storage region (24b) is made to project to the highest position above a substrate on which it is formed. A coating of an organic insulating film (29) is then applied to produce a flat surface. The entire surface of the organic film is then etched to expose the projections (A) of the first metallic electrode (28a) and a second metallic electrode (28b) constituting a pixel electrode is connected to the first electrode (28a) at the exposed portion thereof.

摘要翻译： 当制造“两级”固态图像拾取装置时，使与电信号存储区（24b）电连接的第一金属电极（28a）的一部分突出到其形成的基板上方的最高位置 。 然后施加有机绝缘膜（29）的涂层以产生平坦表面。 然后蚀刻有机膜的整个表面以暴露第一金属电极（28a）的突起（A），并且构成像素电极的第二金属电极（28b）在暴露部分处连接到第一电极（28a） 它们。

公开(公告)号：EP0421053A2

公开(公告)日：1991-04-10

申请号：EP90110403.4

申请日：1990-06-01

申请人： International Business Machines Corporation

发明人： Previti-Kelly, Rosemary Ann

IPC分类号： H01L21/027 ,  G03F7/038

CPC分类号： H01L21/28 ,  H01L21/0272 ,  Y10S148/075 ,  Y10S148/10 ,  Y10S438/951

摘要： Disclosed is a process for forming a pattern of metallization (3) on a processed semiconductor substrate (1), under high temperature conditions, employing a polyimide precursor material (2) as a lift-off layer. Advantageously, the material is photosensitive, and, after exposure and development, the portions of the layer remaining on the substrate can be completely and readily removed with con­ventional solvents.

摘要翻译： 公开了一种在高温条件下，使用聚酰亚胺前体材料（2）作为剥离层，在经处理的半导体衬底（1）上形成金属化图案（3）的工艺。 有利地，材料是光敏的，并且在曝光和显影之后，残留在基底上的层的部分可以用常规溶剂完全和容易地除去。

公开(公告)号：EP0146789B1

公开(公告)日：1990-09-26

申请号：EP84114122.9

申请日：1984-11-23

申请人： International Business Machines Corporation

发明人： Goth, George Richard ,  Hansen, Thomas Adrian ,  Villetto, Robert Thomas, Jr.

IPC分类号： H01L21/308 ,  H01L21/306 ,  H01L21/76

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/76224 ,  Y10S148/011 ,  Y10S148/075

公开(公告)号：EP0139366B1

公开(公告)日：1988-10-12

申请号：EP84305337.2

申请日：1984-08-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Harada, Nozomu Patent Division Toshiba Corp. ,  Komatsubara, Yoshiaki Patent Division

IPC分类号： H01L21/90 ,  H01L27/14

CPC分类号： H01L27/14893 ,  H01L27/14806 ,  Y10S148/075 ,  Y10S148/172

公开(公告)号：EP0146789A2

公开(公告)日：1985-07-03

申请号：EP84114122.9

申请日：1984-11-23

申请人： International Business Machines Corporation

发明人： Goth, George Richard ,  Hansen, Thomas Adrian ,  Villetto, Robert Thomas, Jr.

IPC分类号： H01L21/308 ,  H01L21/306 ,  H01L21/76

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/76224 ,  Y10S148/011 ,  Y10S148/075

摘要： A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls (94) by precluding significant variation in etch bias during the trench formation.
This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.

公开(公告)号：EP0573134B1

公开(公告)日：1998-04-01

申请号：EP93300153.9

申请日：1993-01-11

申请人： INTEL CORPORATION

发明人： Fassberg, Maxine ,  Bost, Melton C. ,  Murali, Krishnamurthy ,  Charvat, Peter K. ,  Price, Lynn A. ,  Linsted , Robert

IPC分类号： H01L23/28 ,  H01L21/312

CPC分类号： H01L24/03 ,  H01L21/02118 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/76802 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10S148/075 ,  H01L2924/00

摘要： A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.

公开(公告)号：EP0573134A1

公开(公告)日：1993-12-08

申请号：EP93300153.9

申请日：1993-01-11

申请人： INTEL CORPORATION

发明人： Fassberg, Maxine ,  Bost, Melton C. ,  Murali, Krishnamurthy ,  Charvat, Peter K. ,  Price, Lynn A. ,  Linsted , Robert

IPC分类号： H01L23/28 ,  H01L21/312

CPC分类号： H01L24/03 ,  H01L21/02118 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/76802 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10S148/075 ,  H01L2924/00

摘要： A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.

摘要翻译： 在半导体衬底上形成保护性聚酰亚胺层的方法包括以下步骤：在随后暴露于显影剂时足以降低酸层蚀刻速率的温度下固化沉积的聚酰胺酸层。 在聚酰胺酸上形成光致抗蚀剂掩模层之后，将基板暴露于显影剂以在其中限定多个焊盘开口。 显影剂渗透到酸层中以在开口下方的区域中形成盐。 随后的硬烘烤酰亚胺化聚酰胺酸，而不是盐区。 去除光致抗蚀剂层还形成聚酰亚胺，其除去盐区域以暴露下面的接合焊盘。

公开(公告)号：EP0421053A3

公开(公告)日：1992-06-10

申请号：EP90110403.4

申请日：1990-06-01

申请人： International Business Machines Corporation

发明人： Previti-Kelly, Rosemary Ann

IPC分类号： H01L21/027 ,  G03F7/038

CPC分类号： H01L21/28 ,  H01L21/0272 ,  Y10S148/075 ,  Y10S148/10 ,  Y10S438/951

摘要： Disclosed is a process for forming a pattern of metallization (3) on a processed semiconductor substrate (1), under high temperature conditions, employing a polyimide precursor material (2) as a lift-off layer. Advantageously, the material is photosensitive, and, after exposure and development, the portions of the layer remaining on the substrate can be completely and readily removed with con­ventional solvents.

摘要翻译： 公开了一种在高温条件下，使用聚酰亚胺前体材料（2）作为剥离层，在经处理的半导体衬底（1）上形成金属化图案（3）的工艺。 有利地，材料是光敏的，并且在曝光和显影之后，残留在基底上的层的部分可以用常规溶剂完全和容易地除去。

公开(公告)号：EP0146789A3

公开(公告)日：1988-03-16

申请号：EP84114122

申请日：1984-11-23

申请人： International Business Machines Corporation

发明人： Goth, George Richard ,  Hansen, Thomas Adrian ,  Villetto, Robert Thomas, Jr.

IPC分类号： H01L21/308 ,  H01L21/306 ,  H01L21/76

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/76224 ,  Y10S148/011 ,  Y10S148/075

摘要： A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls (94) by precluding significant variation in etch bias during the trench formation. This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.