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118 条记录 (耗时 0.017 秒)

    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP3916806A1

    公开(公告)日：2021-12-01

    申请号：EP20869538.7

    申请日：2020-08-31

    申请人： Fuji Electric Co., Ltd.

    发明人： SATO Shigeki ,  ARAKI Ryu ,  MIYATA Hiroshi ,  YOSHIDA Soichi

    IPC分类号： H01L29/78 ,  H01L21/329 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/739 ,  H01L29/866

    摘要： A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The bidirectional diode unit may be arranged between the anode pad and the cathode pad on the front surface.

    ZENERDIODE, ZENERDIODENSCHALTUNG UND VERFAHREN ZUR HERSTELLUNG EINER ZENERDIODE
    6.
    发明授权
    ZENERDIODE, ZENERDIODENSCHALTUNG UND VERFAHREN ZUR HERSTELLUNG EINER ZENERDIODE 有权
    用于生产的齐纳齐纳二极管，齐纳二极管的电路和方法

    公开(公告)号：EP1456890B1

    公开(公告)日：2009-04-29

    申请号：EP02805320.5

    申请日：2002-12-12

    申请人： Austriamicrosystems AG

    发明人： UNTERLEITNER, Franz

    IPC分类号： H01L29/866 ,  H01L21/329

    CPC分类号： H01L29/66106 ,  H01L29/866

    摘要： The invention relates to a Zener diode with a semiconductor substrate (1), which comprises a n-type region (2) and a p-type region (3), whereby the doped regions (2, 3) form a lateral p-n junction (4) and the sides of said doped regions (2, 3), facing to each other, have a width (b) which decreases towards the other doped region (2, 3). Said invention also relates to a method for the production of said Zener diode as well as a Zener diode circuit. The flattened ends of the doped regions as well as the choice of a symmetrical arrangement permit alignment errors of the masks to be compensated for.

    Semiconductor device
    7.
    发明公开
    Semiconductor device 审中-公开
    Halbleiterbauelement

    公开(公告)号：EP1906454A2

    公开(公告)日：2008-04-02

    申请号：EP07019157.2

    申请日：2007-09-28

    申请人： Sanyo Electric Co., Ltd. ,  Sanyo Semiconductor Co., Ltd.

    发明人： Kikuchi, Shuichi ,  Okawa, Shigeaki ,  Nakaya, Kiyofumi ,  Tanaka, Shuji

    IPC分类号： H01L29/866 ,  H01L29/872 ,  H01L29/47 ,  H01L29/40 ,  H01L29/06

    CPC分类号： H01L27/0788 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

    摘要： There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers 5, 6 formed in an N-type epitaxial layer 3, N-type cathode diffusion layers 4 formed in the epitaxial layer 3, a P-type third anode diffusion layer 7, 8 formed in the epitaxial layer 3 so as to surround the first and second anode diffusion layers 5, 6 and to extend toward the cathode diffusion layers 4, and a Schottky barrier metal layer 14 formed on the first and second anode diffusion layers 5, 6.

    摘要翻译： 在肖特基势垒二极管中存在反向漏电流变得过大的问题。 本发明的半导体器件包括形成在N型外延层3中的P型第一和第二阳极扩散层5,6，形成在外延层3中的N型阴极扩散层4，P型第三阳极 扩散层7,8形成在外延层3中，以包围第一和第二阳极扩散层5,6并朝向阴极扩散层4延伸，并且形成在第一和第二阳极扩散层上的肖特基势垒金属层14 层5,6。

    LOW-VOLTAGE PUNCH-THROUGH TRANSIENT SUPPRESSOR EMPLOYING A DUAL-BASE STRUCTURE
    9.
    发明授权
    LOW-VOLTAGE PUNCH-THROUGH TRANSIENT SUPPRESSOR EMPLOYING A DUAL-BASE STRUCTURE 失效
    DURCHBRUCHTRANSIERTER低电压下搬运两层BASE

    公开(公告)号：EP0840943B1

    公开(公告)日：2003-01-15

    申请号：EP96917059.6

    申请日：1996-06-03

    申请人： Semtech corporation

    发明人： YU, Bin ,  HU, Chenming ,  KING, Ya-Chin ,  POHLMAN, Jeffrey, T. ,  TRIVEDI, Rita

    IPC分类号： H01L29/861 ,  H01L29/866

    CPC分类号： H01L29/8618 ,  H01L29/861 ,  H01L29/866

    摘要： A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characterisics. The punch-through diode includes a first region comprising an n+ region (12), a second region comprising a p- region abutting the first region, a third region comprising a p+ region (16) abutting the second region, and a fourth region comprising an n+ region (18) abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm , the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm and about 1.0E17 cm . The junction depth of the fourth (n+) region (18) should be greater than about 0.3 um. The thickness of the third (p+) region (16) should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.