公开(公告)号：EP4430661A1

公开(公告)日：2024-09-18

申请号：EP22822153.7

申请日：2022-11-28

申请人： Siemens Aktiengesellschaft

发明人： LASCH, Markus ,  LORZ, Roland ,  PFEIFER, Markus ,  STEGMEIER, Stefan ,  WEISBROD, Erik ,  WERNER, Ronny ,  ZEYSS, Felix

IPC分类号： H01L23/373 ,  H01L23/34 ,  H01L23/498 ,  H05K1/03 ,  H05K3/34

CPC分类号： H05K2201/09820130101 ,  H05K3/3478 ,  H05K2201/1016620130101 ,  H01L23/3735 ,  H05K2201/1002220130101 ,  H05K1/0306 ,  H01L23/34 ,  H01L23/49833 ,  H01L23/49811

公开(公告)号：EP4421868A1

公开(公告)日：2024-08-28

申请号：EP23158107.5

申请日：2023-02-23

申请人： Infineon Technologies AG

发明人： HOHLFELD, Olaf ,  MICHALSKI, Sebastian

IPC分类号： H01L25/07 ,  H01L23/538 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498

CPC分类号： H01L23/5385 ,  H01L25/072 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/053 ,  H01L23/24 ,  H01L2224/3222520130101 ,  H01L2224/7326520130101 ,  H01L2224/4822720130101 ,  H01L2224/4910920130101 ,  H01L2224/4813920130101 ,  H01L24/48

摘要： A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer comprises a plurality of different sections that are separate and distinct from each other, and a plurality of semiconductor bodies arranged on the first metallization layer, wherein a first electrode of each of the plurality of semiconductor bodies is electrically coupled to a first section of the first metallization layer, a second electrode of each of the plurality of semiconductor bodies is electrically coupled to a second section of the first metallization layer, a third electrode of each of the plurality of semiconductor bodies is electrically coupled to an additional metallization layer by means of one or more electrical connection elements, the additional metallization layer is arranged distant from and in parallel to the first metallization layer, and the additional metallization layer is arranged on an additional dielectric insulation layer, wherein the additional dielectric insulation layer is arranged in parallel to and distant from the dielectric insulation layer, and wherein the additional dielectric insulation layer is arranged between the additional metallization layer and the first metallization layer.

公开(公告)号：EP4411995A1

公开(公告)日：2024-08-07

申请号：EP23155082.3

申请日：2023-02-06

申请人： Infineon Technologies AG

发明人： BÖNIG, Guido ,  HOHLFELD, Olaf ,  MICHALSKI, Sebastian

IPC分类号： H01R12/58 ,  H01R13/10 ,  H01R43/16 ,  H01L23/498

CPC分类号： H01L23/49811 ,  H01R43/16 ,  H01R12/585 ,  H01R13/10

摘要： A method comprises stamping a blank from a metal sheet, the blank comprising a first section, and a second section, wherein the second section is an elongated section having a length in a vertical direction that is at least twice its width in a first horizontal direction, and the first section is a rectangular section having a width in the first horizontal direction that is greater than the width of the second section, forming a thread on a surface of the first section, and bending the first section to form a sleeve, wherein the sleeve comprises an opening facing in the vertical direction towards the second section.

公开(公告)号：EP4406016A1

公开(公告)日：2024-07-31

申请号：EP22786221.6

申请日：2022-08-23

申请人： QUALCOMM INCORPORATED

发明人： PATIL, Aniket ,  WE, Hong Bok ,  BUOT, Joan Rey Villarba

IPC分类号： H01L23/498 ,  H01L23/538

CPC分类号： H01L23/49811 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/5383

公开(公告)号：EP3582598B1

公开(公告)日：2024-07-24

申请号：EP19189512.7

申请日：2015-01-30

IPC分类号： H05K7/14 ,  H01L23/498 ,  H01L25/07 ,  H01L23/367

CPC分类号： H01L23/367 ,  H01L2924/000220130101 ,  H01L23/49811 ,  H01L25/072 ,  H05K7/14329

公开(公告)号：EP4371155A1

公开(公告)日：2024-05-22

申请号：EP22741108.9

申请日：2022-06-10

申请人： Qualcomm Incorporated

发明人： VEMURI, Krishna ,  KIM, Jinseong

IPC分类号： H01L25/065 ,  H01L23/538

CPC分类号： H01L23/5383 ,  H01L23/49816 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/5385 ,  H01L2225/0656220130101 ,  H01L2225/0651720130101 ,  H01L2224/8119220130101 ,  H01L2225/0658620130101 ,  H01L2924/1531120130101 ,  H01L2224/1308220130101 ,  H01L2224/1622720130101 ,  H01L2224/1623520130101 ,  H01L2224/13120130101 ,  H01L2224/8181520130101 ,  H01L2224/3214520130101 ,  H01L2224/7325320130101 ,  H01L2224/7320320130101 ,  H01L25/50 ,  H01L24/16 ,  H01L24/81 ,  H01L24/73 ,  H01L24/32 ,  H01L24/13

公开(公告)号：EP3413343A2

公开(公告)日：2018-12-12

申请号：EP18174093.7

申请日：2018-05-24

申请人： Dyconex AG

发明人： Hauer, Marc ,  Bihler, Eckardt ,  Held, Jochen

IPC分类号： H01L23/00 ,  H01L23/498 ,  A61N1/375

CPC分类号： H05K5/065 ,  A61N1/3752 ,  A61N1/3754 ,  H01L23/49811 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/80203 ,  H01L2224/80385 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81898 ,  H01L2224/821 ,  H01L2224/82138 ,  H01L2224/82203 ,  H01L2224/8236 ,  H01L2224/82895 ,  H01L2224/9212 ,  H01L2224/92124 ,  H01L2224/92144 ,  H05K1/028 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/112 ,  H05K1/189 ,  H05K3/285 ,  H05K3/303 ,  H05K3/4076 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2203/1316 ,  H05K2203/1327 ,  H05K2203/166 ,  H05K3/4661 ,  H01L2224/80001 ,  H01L2224/82

摘要： An electronic module (1) on a flexible planar circuit substrate (3) with a conductor configuration (3b) on a first substrate surface and a plurality of electronic components (5)on the opposite, second substrate surface, wherein the components have component contacts (5a), which are electrically connected selectively by way of vias (7) in the circuit substrate (3) and the conductor configuration (3b), wherein the circuit substrate is a thermoplastic polymer and the component contacts (5a) are melted or thermally pressed into the second substrate surface in the region of the vias (7).

公开(公告)号：EP3413342A1

公开(公告)日：2018-12-12

申请号：EP17174971.6

申请日：2017-06-08

申请人： Dyconex AG

发明人： Hauer, Marc ,  Bihler, Eckardt ,  Held, Jochen

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H05K5/065 ,  A61N1/3752 ,  A61N1/3754 ,  H01L23/49811 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/80203 ,  H01L2224/80385 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81898 ,  H01L2224/821 ,  H01L2224/82138 ,  H01L2224/82203 ,  H01L2224/8236 ,  H01L2224/82895 ,  H01L2224/9212 ,  H01L2224/92124 ,  H01L2224/92144 ,  H05K1/028 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/112 ,  H05K1/189 ,  H05K3/285 ,  H05K3/303 ,  H05K3/4076 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2203/1316 ,  H05K2203/1327 ,  H05K2203/166 ,  H05K3/4661 ,  H01L2224/80001 ,  H01L2224/82

摘要： Elektronische Baugruppe auf einem flexiblen flächigen Schaltungssubstrat mit einer Leiterkonfiguration auf einer ersten Substratoberfläche und mehreren elektronischen Bauelementen auf der gegenüberliegenden zweiten Substratoberfläche, wobei die Bauelemente Bauelementkontakte aufweisen, die über Durchkontaktierungen in dem Schaltungssubstrat und die Leiterkonfiguration selektiv elektrisch angeschlossen sind, wobei das Schaltungssubstrat ein thermoplastisches Polymer aufweist und die Bauelementkontakte im Bereich der Durchkontaktierungen in die zweite Substratoberfläche eingeschmolzen bzw. thermisch eingepresst sind.

公开(公告)号：EP3381052A1

公开(公告)日：2018-10-03

申请号：EP16762778.5

申请日：2016-09-06

申请人： SnapTrack, Inc.

发明人： SCHMAJEW, Alexander

IPC分类号： H01L23/498 ,  H01L23/485 ,  H01L21/60 ,  H01L21/56 ,  B81C3/00

CPC分类号： H01L24/16 ,  B81C3/00 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/1132 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/00012

摘要： The invention relates to an electrical module (EB) and to a method for producing an electrical module (EB). The module (EB) has a substrate (TR) with an upper layer (O) and a metal contact surface (MK) arranged thereon, as well as a solder resist layer (LSS) that covers part of the upper side (O), but not the contact surface (MK). The module (EB) also comprises an electrical component (EK) with a contact surface (KF) on the lower side and a solder bump connection (BU) that connects the two contact surfaces (MK, KF). The solder resist layer (O) has a maximum thickness of 200 nm and thereby simplifies subsequent method steps for the encapsulation of the module (EB) with a mould mass (MM).

公开(公告)号：EP3378290A1

公开(公告)日：2018-09-26

申请号：EP16806407.9

申请日：2016-11-18

申请人： Raytheon Company

发明人： WONG, Tse E. ,  CHEN, Shea ,  CHOE, Hoyoung C.

IPC分类号： H05K1/02 ,  H01L23/498 ,  H05K3/34

CPC分类号： H05K1/0271 ,  H01L23/4924 ,  H01L23/49534 ,  H01L23/49544 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L25/065 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/0305 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/094 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/047 ,  Y02P70/613

摘要： A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.