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    TECHNOLOGIES FOR QUALITY OF SERVICE BASED THROTTLING IN FABRIC ARCHITECTURES
    5.
    发明公开
    TECHNOLOGIES FOR QUALITY OF SERVICE BASED THROTTLING IN FABRIC ARCHITECTURES 审中-公开

    公开(公告)号：EP3790240A1

    公开(公告)日：2021-03-10

    申请号：EP20203476.5

    申请日：2017-03-02

    申请人： INTEL Corporation

    发明人： Bernat, Francesc G. ,  Kumar, Karthik ,  Willhalm, Thomas ,  Ramanujan, Raj K. ,  Slechta, Brian

    IPC分类号： H04L12/813 ,  H04L12/931 ,  H04L12/933 ,  G06F12/0806

    摘要： Disclosed in the present disclosure is an apparatus comprising a first multi-chip package. The first multi-chip package comprises: a first plurality of cores, a first interconnect coupled to the first plurality of cores, an interconnect link to transmit data, a second interconnect coupled to the first interconnect via the interconnect link, a first memory interconnect to couple the first plurality of cores to a first system memory device, the first plurality of cores to access the first memory interconnect via the first interconnect, the interconnect link, and the second interconnect. The first memory interconnect and first system memory device are to be associated with a first non-uniform memory access (NUMA) domain. A first multi-chip package is coupled to a second multi-chip package associated with a second NUMA domain. A first NUMA domain identifier is to be associated with the first NUMA domain and a second NUMA domain identifier is to be associated with the second NUMA domain. The first multi-chip package further comprises: monitoring circuitry for monitoring utilization of a resource associated with the first NUMA domain, the monitoring circuitry including one or more model-specific registers, MSRs, to store counter values associated with requests to access the resource, and enforcement circuitry for limiting utilization of the resource from within the first NUMA domain or from the second NUMA domain in accordance with one or more of the counter values. The counter values include a first counter value associated with utilization of the resource from within the first NUMA domain and a second counter value associated with utilization of the resource from at least the second NUMA domain.

    CACHE DATA MIGRATION IN A MULTICORE PROCESSING SYSTEM
    7.
    发明授权
    CACHE DATA MIGRATION IN A MULTICORE PROCESSING SYSTEM 有权

    公开(公告)号：EP2880539B1

    公开(公告)日：2018-09-12

    申请号：EP13737941.8

    申请日：2013-07-01

    申请人： Qualcomm Incorporated

    发明人： LIANG, Jian ,  SHEN, Jian

    IPC分类号： G06F12/0806 ,  G06F12/0893

    CPC分类号： G06F12/0806 ,  G06F12/0893 ,  Y02D10/13

    摘要： A method of transferring data between two caches comprises sending a first message from a first processor to a second processor indicating that data is available for transfer from a first cache associated with the first processor, requesting, from the second processor, a data transfer of the data from the first cache to a second cache associated with the second processor, transferring the data from the first cache to the second cache in response to the request, and sending a second message from the second processor to the first processor indicating that the data transfer is complete.