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79 条记录 (耗时 0.022 秒)

    METHOD AND APPARATUS FOR VERIFYING PLACEMENT OF CHIP COMPONENT ON PRINTED CIRCUIT BOARD
    4.
    发明公开
    METHOD AND APPARATUS FOR VERIFYING PLACEMENT OF CHIP COMPONENT ON PRINTED CIRCUIT BOARD 审中-实审

    公开(公告)号：EP4435662A1

    公开(公告)日：2024-09-25

    申请号：EP24160504.7

    申请日：2024-02-29

    申请人： Samsung SDI Co., Ltd.

    发明人： Lee, Eunsik

    IPC分类号： G06F30/398 ,  G06F30/392 ,  G06F115/12 ,  G06F119/18

    CPC分类号： G06F30/392 ,  G06F2115/1220200101 ,  G06F2119/1820200101 ,  G06F30/398

    摘要： Provided is a method of verifying component placement on a printed circuit board, PCB, the method including obtaining a preset separation distance criterion for an arrangement of chip components (10) designed to be mounted on the PCB, and based on the preset separation distance criterion for the arrangement of the chip components, checking whether a separation distance (5) between the chip components (10) satisfies the preset separation distance criterion, wherein the checking of whether the preset separation distance criterion is satisfied includes verifying, based on the preset separation distance criterion, whether the separation distance (5) between the chip components (10) that are placed to alternate with each other satisfies the preset separation distance criterion.

    CHIP LAYOUT WIRING METHOD AND APPARATUS, DEVICE, STORAGE MEDIUM AND CHIP LAYOUT
    5.
    发明公开
    CHIP LAYOUT WIRING METHOD AND APPARATUS, DEVICE, STORAGE MEDIUM AND CHIP LAYOUT 审中-实审

    公开(公告)号：EP4421672A1

    公开(公告)日：2024-08-28

    申请号：EP23845012.6

    申请日：2023-05-18

    申请人： Tencent Technology (Shenzhen) Company Limited

    发明人： MA, Shengming ,  CHEN, Yue ,  WANG, Jianming ,  HUAI, Sainan ,  ZHANG, Shengyu ,  WANG, Xuemeng ,  XU, Xiong ,  LI, Yanghepu

    IPC分类号： G06F30/392

    CPC分类号： G06F30/392 ,  G06F30/394

    摘要： The present application discloses a chip layout wiring method and apparatus, a device, a storage medium and a chip layout, and relates to the technical field of chips. The method comprises: acquiring a chip layout to be wired, and wiring planning information corresponding to the chip layout; the wiring planning information comprising planning information for a first point location in the chip layout, the planning information of the first point location being used for defining a location area, wiring orientation, and planning track of the first point location, and a first end of the planning track being connected to the first point location (410); according to the location area and the wiring orientation, providing a second point location for connecting the chip layout, and a first wiring segment for a second end of the planning track (420); according to the planning track, arranging a second end connected to the planning track, and a second wiring segment of the first point location (430); and according to the first wiring segment and the second wiring segment, arranging connection wiring (440) between the second point location and the first point location. The present application can achieve automatic wiring and improves the accuracy of automatic wiring.

    INTEGRATED CIRCUIT INCLUDING SWITCH CELL AREA
    6.
    发明公开
    INTEGRATED CIRCUIT INCLUDING SWITCH CELL AREA 审中-公开

    公开(公告)号：EP4401134A1

    公开(公告)日：2024-07-17

    申请号：EP23220349.7

    申请日：2023-12-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： YU, Jisu ,  DO, Jungho ,  JUNG, Sungyup

    IPC分类号： H01L23/528 ,  G06F30/392 ,  H01L27/02 ,  H01L27/118

    CPC分类号： H01L23/5286 ,  H01L27/0207 ,  H01L27/118 ,  G06F30/392 ,  H01L27/11807

    摘要： An integrated circuit includes: a plurality of first power rails extending in a first horizontal direction and configured to provide a first power supply voltage that is applied thereto; a plurality of second power rails extending in the first horizontal direction and configured to provide a second power supply voltage that is applied thereto; and a power line in a switch cell area and extending in the first horizontal direction the power line being configured to provide a global power supply voltage that is applied thereto, wherein the plurality of first power rails and the plurality of second power rails are alternately arranged in a second horizontal direction vertical to the first horizontal direction, wherein the plurality of first power rails, the plurality of second power rails, and the power line form a front-side pattern on a same layer, and wherein the power line is provided between two second power rails adjacent to each other in the first horizontal direction, among the plurality of second power rails.

    STATIC RANDOM ACCESS MEMORY ARRAY PATTERN
    8.
    发明公开
    STATIC RANDOM ACCESS MEMORY ARRAY PATTERN 审中-公开

    公开(公告)号：EP4294144A1

    公开(公告)日：2023-12-20

    申请号：EP22187031.4

    申请日：2022-07-26

    申请人： United Microelectronics Corp.

    发明人： HUANG, Chun-Hsien ,  KUO, Yu-Tse ,  WANG, Shu-Ru ,  HUANG, Li-Ping ,  TSENG, Chun-Yen

    IPC分类号： H10B10/00 ,  H01L27/02 ,  G06F30/392

    摘要： The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.