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    COMPUTER-IMPLEMENTED METHOD OF EXECUTING AN ARITHMETIC OR LOGIC OPERATION IN COMBINATION WITH AN ACCUMULATE OPERATION AND PROCESSOR
    2.
    发明公开
    COMPUTER-IMPLEMENTED METHOD OF EXECUTING AN ARITHMETIC OR LOGIC OPERATION IN COMBINATION WITH AN ACCUMULATE OPERATION AND PROCESSOR 审中-公开

    公开(公告)号：EP3835938A1

    公开(公告)日：2021-06-16

    申请号：EP19215342.7

    申请日：2019-12-11

    申请人： Unify Patente GmbH & Co. KG

    发明人： BERNARDI, Paulo ,  SAMSONIUK, Marcelo

    IPC分类号： G06F5/01 ,  G06F7/544

    摘要： The present invention relates to a computer-implemented method of executing an arithmetic or logic operation (4) in combination with an accumulate operation in an arithmetic logic unit, ALU, (1) wherein the method comprises the steps of receiving a first element (2) and a second element (2') at the ALU (1) and combining the first and second elements (2, 2') in the ALU (1) according to the arithmetic or logic operation (4), performing an accumulate operation on the result of the combined first and second elements in an accumulator unit (3) via an add logic (8) of the ALU (1) and a feedback path (5) leading from the accumulator unit (3) to the add logic (8), performing a first shift operation on the accumulated result, wherein the method further comprises the step of performing a second shift operation in the feedback path (5), wherein the second shift operation is defined by an operator (4') that determines the direction of the shift and the number of bits to be shifted in a barrel shifter, wherein all steps are executed in one single clock. Further, the present invention relates to a processor, comprising an ALU (1), the ALU (1) being adapted to execute an arithmetic operation or logic operation (4) in combination with an accumulate operation in one single clock, wherein the ALU (1) is adapted to carry out the method of executing an arithmetic or logic operation (4) in combination with an accumulate operation.

    FULLY DIGITAL CHAOTIC DIFFERENTIAL EQUATION-BASED SYSTEMS AND METHODS
    7.
    发明公开
    FULLY DIGITAL CHAOTIC DIFFERENTIAL EQUATION-BASED SYSTEMS AND METHODS 有权
    全数字混沌微分方程的系统和方法

    公开(公告)号：EP2681672A2

    公开(公告)日：2014-01-08

    申请号：EP12752689.5

    申请日：2012-02-29

    申请人： King Abdullah University Of Science And Technology

    发明人： RADWAN, Ahmed, Gomaa, Ahmed ,  ZIDAN, Mohammed, Affan ,  SALAMA, Khaled, N.

    IPC分类号： G06F17/13 ,  G06F7/48 ,  G06F5/01 ,  G06F7/58 ,  G06F17/10

    CPC分类号： G06F7/588 ,  G06F7/58 ,  G06F7/586 ,  H04L9/001 ,  H04L9/0656

    摘要： Various embodiments are provided for fully digital chaotic differential equation- based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

    摘要翻译： 为全数字混沌微分方程系统和方法提供了各种实施例。 在其中一个实施例中，数字电路包括数字状态寄存器和一个或多个数字逻辑模块，其被配置为从两个或更多个数字状态寄存器获得第一值; 基于所获得的第一值和混沌微分方程来确定第二值; 并提供第二值以设定多个数字状态寄存器之一的状态。 在另一个实施例中，数字电路包括数字状态寄存器，被配置为从数字移位寄存器的子集获得输出并且基于混沌微分方程来提供输入的数字逻辑模块，用于设置子集的至少一个 数字移位寄存器，以及配置成提供用于操作数字移位寄存器的时钟信号的数字时钟。

    Arithmetic shifter, processor unit and storage device
    8.
    发明公开
    Arithmetic shifter, processor unit and storage device 审中-公开
    Arithmetischer Schieber，Prozessoreinheit und Speichervorrichtung

    公开(公告)号：EP1696314A1

    公开(公告)日：2006-08-30

    申请号：EP06000180.7

    申请日：2006-01-05

    申请人： Hitachi Global Storage Technologies Netherlands B.V.

    发明人： Dobbek, Jeffrey J. ,  Hwang, Kirk

    IPC分类号： G06F5/01

    CPC分类号： G11B20/10 ,  G06F5/01 ,  G06F7/49921 ,  G11B2220/2516

    摘要： A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit is combined with an arithmetic shifter and a final decision multiplexor. The final decision multiplexor receives the output from the arithmetic shifter and the saturated value from the saturation circuit. When saturation is detected by the saturation detection circuit, the final decision multiplexor selects the saturate minimum or the saturate maximum depending on whether the MSB of the data in equals one or zero, respectively.

    摘要翻译： 公开了一种为数字信号处理器操作提供饱和的移位过程的方法，装置和程序存储装置。 产生用于将操作数移位到最大值或最小值的指令，这取决于饱和发生时输入的数据位。 饱和检测电路与算术移位器和最终决策多路复用器组合。 最终决策多路复用器接收来自算术移位器的输出和饱和电路的饱和值。 当饱和检测电路检测到饱和时，最终判决多路复用器根据数据的MSB分别等于1或零，分别选择饱和最小值或饱和最大值。

    DATA CALCULATING DEVICE
    10.
    发明公开
    DATA CALCULATING DEVICE 有权
    数据计算设备

    公开(公告)号：EP1094401A4

    公开(公告)日：2002-06-19

    申请号：EP99925312

    申请日：1999-06-14

    申请人： ASAHI CHEMICAL IND ,  SYSTEMONIC AG

    发明人： KOBAYASHI SHIRO ,  FETTWEIS GERHARD

    IPC分类号： G06F7/50 ,  G06F7/57 ,  G06F17/10 ,  G06F5/01

    CPC分类号： G06F7/483 ,  G06F7/485 ,  G06F7/49936 ,  G06F7/509

    摘要： A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating system. Each piece of data of a data group is calculated, the minimum scale factor representative of the calculated data is detected as a group scale factor (GSF), and calculated data is subjected to scaling based on the detected GSFs. These processing are applied to each data group of a data block. The minimum GSF out of the detected GSFs is detected as a block scale factor (BSF). When calculation of the calculated data is performed again, the calculated data of the data group is subjected to scaling according to the GSFs and BSF before the calculation performed again.