中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

757 records (took 0.018 seconds)

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：EP4489008A1

    公开(公告)日：2025-01-08

    申请号：EP23220745.6

    申请日：2023-12-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KIM, Dongha ,  HONG, Seungki ,  PARK, Youngjae ,  KIM, Dohan

    IPC: G11C29/18 ,  G11C11/4078 ,  G11C29/42 ,  G11C29/52 ,  G06F11/10 ,  G11C11/406 ,  G11C29/04 ,  G11C29/12 ,  G11C29/20

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.

    SYSTEM FOR REFRESHING DYNAMIC RANDOM ACCESS MEMORY
    3.
    发明公开
    SYSTEM FOR REFRESHING DYNAMIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：EP4386754A1

    公开(公告)日：2024-06-19

    申请号：EP23211133.6

    申请日：2023-11-21

    Applicant: NXP B.V.

    Inventor： Chakravarty, Suhas ,  Welker, James Andrew

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40618 ,  G11C11/40622 ,  G11C11/40611 ,  G06F13/1636 ,  G11C11/40603 ,  G11C2211/406220130101

    Abstract: A refresh circuit selects a candidate bank for refreshing from various banks of a dynamic random access memory (DRAM). Initially, the refresh circuit checks if any bank is idle (e.g., is not targeted for memory operations). If two or more banks are idle, the candidate bank is selected based on a count of accesses targeted to each occupied bank and bank-pair distances between each pair of idle and occupied banks. Conversely, if all banks are occupied, the refresh circuit selects the candidate bank based on a count of data accesses targeted to each bank and/or a count of parity accesses targeted to each bank. Each data access has the same type as that scheduled for execution on the DRAM. Once the candidate bank is selected, the refresh circuit triggers the refresh of the candidate bank.

    REFRESH ADDRESS COUNTING CIRCUIT AND METHOD, REFRESH ADDRESS READ-WRITE CIRCUIT, AND ELECTRONIC DEVICE
    6.
    发明公开
    REFRESH ADDRESS COUNTING CIRCUIT AND METHOD, REFRESH ADDRESS READ-WRITE CIRCUIT, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：EP4287188A1

    公开(公告)日：2023-12-06

    申请号：EP22857334.1

    申请日：2022-04-29

    Applicant: Changxin Memory Technologies, Inc.

    Inventor： FAN, Xian ,  GU, Yinchuan ,  CAO, Xianlei ,  YANG, Yu ,  SU, HSIN-CHENG

    IPC: G11C11/406 ,  G11C11/409

    Abstract: A refresh address counting circuit, a refresh address counting method, a refresh address read-write circuit, and an electronic device, which relate to the technical field of integrated circuits. The refresh address counting circuit comprises: a self-oscillation clock generation module, used for generating, within each refresh cycle, a self-oscillation clock signal based on an array activation signal after a refresh signal is obtained; a self-oscillation mask module, used for generating a self-oscillation mask signal under a preset refresh command; and a refresh address counting module, used for counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and outputting a self-oscillation refresh address. Provided is a refresh address counting circuit suitable for DDR5.

Patent Agency Ranking