公开(公告)号：EP4154252B1

公开(公告)日：2024-11-13

申请号：EP20825031.6

申请日：2020-11-18

Inventor： FRULIO, Massimiliano

IPC: G11C7/06 ,  G11C7/08 ,  G11C16/28 ,  H03K19/21

公开(公告)号：EP3662473B1

公开(公告)日：2024-09-04

申请号：EP18840725.8

申请日：2018-07-30

IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4093 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03146 ,  H04L7/0079 ,  G11C7/1084 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4093

公开(公告)号：EP4418268A1

公开(公告)日：2024-08-21

申请号：EP23191931.7

申请日：2023-08-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Pasupula, Suresh ,  Dwivedi, Devesh

IPC: G11C7/06

CPC classification number: G11C7/065

Abstract: Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2~1/2∗VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.

公开(公告)号：EP3907737B1

公开(公告)日：2024-08-21

申请号：EP21166023.8

申请日：2021-03-30

IPC: G11C7/08 ,  G11C7/06 ,  G11C11/419

CPC classification number: G11C7/08 ,  G11C11/419 ,  G11C7/065

公开(公告)号：EP4042422B1

公开(公告)日：2024-07-10

申请号：EP20917463.0

申请日：2020-02-06

IPC: G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  H03F3/45

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2203/4561420130101 ,  H03F2203/4556220130101 ,  H03F2203/4558820130101

公开(公告)号：EP4383258A1

公开(公告)日：2024-06-12

申请号：EP23156987.2

申请日：2023-02-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： HUNG, Chun-Hsiung ,  LIANG, Fu-Nian ,  YANG, Shang-Chi

IPC: G11C7/14 ,  G11C16/28 ,  G11C7/06

CPC classification number: G11C16/28 ,  G11C7/14 ,  G11C7/062

Abstract: Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

公开(公告)号：EP4338158A1

公开(公告)日：2024-03-20

申请号：EP22723917.5

申请日：2022-04-28

Applicant: QUALCOMM Incorporated

Inventor： RASMUS, Todd Morgan

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/10 ,  H03K5/24 ,  H03M9/00 ,  H04L25/02

公开(公告)号：EP4325493A1

公开(公告)日：2024-02-21

申请号：EP22782813.4

申请日：2022-07-25

Applicant: Changxin Memory Technologies, Inc.

Inventor： LIN, Feng

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

Abstract: Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal; and a third NMOS transistor and a fourth NMOS transistor, the third NMOS transistor being provided with one terminal connected to the third node and another terminal connected to one terminal of the fourth NMOS transistor, another terminal of the fourth NMOS transistor being connected to the fourth node, a gate of one of the third NMOS transistor and the fourth NMOS transistor being configured to receive a second complementary feedback signal, and a gate of the other one of the third NMOS transistor and the fourth NMOS transistor being configured to receive the enable signal; and a second amplification module. The embodiments of the present disclosure at least facilitate accelerating the processing speed of the circuit for receiving data to the data signal while improving the receiving performance of the circuit for receiving data.

公开(公告)号：EP4092673B1

公开(公告)日：2024-01-31

申请号：EP21859351.5

申请日：2021-07-21

Inventor： SU, Hsin-cheng

IPC: G11C29/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C5/14 ,  G11C11/4074

公开(公告)号：EP4210054A1

公开(公告)日：2023-07-12

申请号：EP22211046.2

申请日：2022-12-02

Applicant: STMicroelectronics S.r.l.

Inventor： DISEGNI, Fabio Enrico Carlo ,  CARISSIMI, Marcella ,  TOMASONI, Alessandro ,  LO IACONO, Daniele

IPC: G11C7/06 ,  G11C13/00

Abstract: A sense amplifier architecture (10) for a memory device (1) having a plurality of memory cells (3), wherein groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high ('1') or logic low ('0'), of the memory cells of the group; the sense amplifier architecture (10) has: a plurality of sense amplifier reading branches (15), each sense amplifier reading branch (15) coupled to a respective memory cell (3) and configured to provide an output signal (sCOMP_A), which is indicative of a cell current (I cell ) flowing through the same memory cell (3); a comparison stage (12), to perform a comparison between the cell currents (I cell ) of memory cells (3) of a group; and a logic stage (13), to determine, based on comparison results provided by the comparison stage (12), a read codeword corresponding to the group of memory cells (3). Information may be stored in different subsets (SB1, SB2) of codewords, the sense amplifier architecture (10) in this case having a subset definition circuit (40), to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.