公开(公告)号：JP5934379B2

公开(公告)日：2016-06-15

申请号：JP2014542318

申请日：2012-10-22

Applicant: シリコン ストーリッジ テクノロージー インコーポレイテッド ,  SILICON STORAGE TECHNOLOGY, INC.

Inventor： ガザヴィ パーヴィス ,  トラン ヒュー ヴァン ,  ワン シウ−ルーン ,  ドー ニャン ,  オンマニ ヘンリー エイ

IPC: H01L27/115 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8247

CPC classification number: H01L27/0207 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

公开(公告)号：JP5144026B2

公开(公告)日：2013-02-13

申请号：JP2006129028

申请日：2006-05-08

Applicant: シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： ガオ フェン ,  フェン リン ヤー ,  ダブリュー クックシー ジョン ,  チェン チャンユアン ,  ウィッドジャジャ ユニアート ,  リー ダナ

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

公开(公告)号：JP4388266B2

公开(公告)日：2009-12-24

申请号：JP2002321647

申请日：2002-11-05

Applicant: シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： シン ワン チー

IPC: H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array and a peripheral region adjacent the array containing related logic devices. Structure planarization is enhanced by utilizing a pattern of dummy material in the peripheral region. The control gates of the memory cells and the logic gates of the logic devices are formed separately so each can be independently optimized.

公开(公告)号：JP2009044164A

公开(公告)日：2009-02-26

申请号：JP2008225276

申请日：2008-08-06

Applicant: Silicon Storage Technology Inc ,  シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： LIU XIANG ,  LEVI AMITAY ,  KOTOV ALEXANDER ,  TKACHEV YURI ,  MARKOV VIKTOR ,  JIA JAMES YINGBO ,  SU CHIEN-SHENG ,  HU YAW WEN

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: PROBLEM TO BE SOLVED: To improve the efficiency of erasing a cell by the specific dimensional relation of an erase gate with a floating gate.
SOLUTION: An improved split gate type non-volatile memory cell having in a substrate a second conductivity first region, a second conductivity second region, and a channel region between the first region and the second region is formed in a substantially single crystal substrate of the first conductivity type. The cell has a selection gate on the upper portion of the channel region, a floating gate on another portion of the channel, a control gate on the floating gate, and an erase gate adjoining the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang against the dimension of a separation in the vertical direction between the floating gate and the erase gate is in between about 1.0 and 2.5.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过擦除栅极与浮动栅极的特定尺寸关系来提高擦除单元的效率。 解决方案：在基板中具有第二导电性第一区域，第二导电性第二区域和第一区域与第二区域之间的沟道区域的改进的分离栅极型非易失性存储单元形成为基本单晶 第一导电类型的衬底。 信道在信道区域的上部具有选择栅极，沟道的另一部分上的浮动栅极，浮置栅极上的控制栅极以及与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直方向上的间隔尺寸的比率在约1.0和2.5之间。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009005364A

公开(公告)日：2009-01-08

申请号：JP2008167906

申请日：2008-05-30

Applicant: Silicon Storage Technology Inc ,  シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： DENG CHRISTOPHER ,  ELGORRIAGA IGOR ,  YI FAN ,  CHANG MAU-CHUNG FRANK

IPC: H04L29/02 ,  H04B7/02 ,  H04B7/06 ,  H04B7/12

CPC classification number: H04L65/608 ,  H04L1/1607

Abstract: PROBLEM TO BE SOLVED: To provide a method for transmitting and receiving a digital audio signal having a first plurality of blocks, in which each block has a second plurality of frames, each frame has a third plurality of sub-frames, and each sub-frame has preamble and binary data. SOLUTION: In this method, the sub-frame is a first sub-frame of the frame, and the frame is a first frame of the block, and preamble is searched in relation to the sub-frame. Then, the digital audio signal is transmitted efficiently and re-configured by each stages, where only binary data of each sub-frame are transmitted at each frame, and after that, the transmission is performed at each block. In a desirable embodiment, the transmission protocol of the data requires each data packet so as to perform transmission with 512 bytes. The data packet transmitted by a transmitter should be checked by an acknowledgement response (ACK) packet send from a receiver. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种发送和接收具有第一多个块的数字音频信号的方法，其中每个块具有第二多个帧，每个帧具有第三多个子帧，并且 每个子帧具有前导码和二进制数据。 解决方案：在该方法中，子帧是帧的第一子帧，帧是块的第一帧，并且相关于子帧搜索前导码。 然后，数字音频信号被有效地发送并由每一级重新配置，其中在每个帧仅发送每个子帧的二进制数据，之后在每个块执行发送。 在期望的实施例中，数据的传输协议需要每个数据分组以便执行512字节的传输。 由发射机发送的数据包应通过从接收机发送的确认响应（ACK）包进行检查。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006332641A

公开(公告)日：2006-12-07

申请号：JP2006129291

申请日：2006-05-08

Applicant: Silicon Storage Technology Inc ,  シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： WIDJAJA YUNIARTO ,  COOKSEY JOHN W ,  CHEN CHANGYUAN ,  GAO FENG ,  LIN YA-FEN ,  LEE DANA

IPC: H01L21/8247 ,  G11C16/02 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

Abstract: PROBLEM TO BE SOLVED: To improve the pitch of a nonvolatile memory device by reducing the number of lines for each cell, in a NAND flash memory structure. SOLUTION: A split gate NAND flash memory structure is formed on a first conductive type semiconductor substrate. This NAND structure is provided with a first region of a second conductive type in the substrate; and a second region of a second conductive type, that is spaced apart from the first region in the substrate. A first channel region that is continuous is defined between the first region and the second region. A plurality of floating gates are spaced apart from each another, and each of a plurality of floating gates is arranged on the separate parts of the channel region. There are provided a plurality of control gates that are each associated with one floating gate and adjacent to the floating gate. Each control gate has two parts, that is, a first part located on the part of the channel region and a second part, located on the associated floating gate and capacitively connected to the floating gate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过减少NAND单元中的线数来提高非易失性存储器件的间距，在NAND闪速存储器结构中。 解决方案：在第一导电类型半导体衬底上形成分裂栅极NAND闪速存储器结构。 该NAND结构在衬底中设置有第二导电类型的第一区域; 以及与衬底中的第一区域间隔开的第二导电类型的第二区域。 在第一区域和第二区域之间限定连续的第一沟道区域。 多个浮动栅极彼此间隔开，并且多个浮动栅极中的每一个布置在沟道区域的分离部分上。 提供了多个控制栅极，每个控制栅极与一个浮动栅极相关联并且与浮动栅极相邻。 每个控制栅极具有两个部分，即位于沟道区域的一部分上的第一部分和位于相关联的浮动栅极上并电容连接到浮动栅极的第二部分。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004312021A

公开(公告)日：2004-11-04

申请号：JP2004112443

申请日：2004-04-06

Applicant: Silicon Storage Technology Inc ,  シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： CHEN BOMY ,  KIANIAN SOHRAB ,  FRAYER JACK

IPC: G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To provide a high density, bidirectional reading/programming nonvolatile memory cell and its array.
SOLUTION: Each memory cell (15) has two separated floating gates (40a, 40b) for storing charges, and source/drain regions (52a, 52b) separated by a channel having three parts. Each floating gate exists above the first part and the second part, a gate electrode (62) exists above the third part of the channel located between them and controls conduction. Independently controllable control gates (54a, 54b) are insulated from the source/drain region and coupled capacitively with the floating gate. A cell is programmed by hot channel electron injection and erased by Fowler Nordheim tunneling of electrons from the floating gate to the gate electrode. Such a program as the cell stores 1 bit in each floating gate by bidirectional reading is thereby realized. The control gate operates a cell array in NAND arrangement.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004289161A

公开(公告)日：2004-10-14

申请号：JP2004082034

申请日：2004-03-22

Applicant: Silicon Storage Technology Inc ,  シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc.

Inventor： CHEN BOMY ,  TSUI YING KIT ,  LU WEN-JUEI

IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

Abstract: PROBLEM TO BE SOLVED: To provide an array of floating gate memory cells having a trench formed in the surface of a semiconductor substrate. SOLUTION: A source region is formed beneath a trench, a drain region is formed along the surface of a substrate, and a channel region between them includes a first part stretching vertically along the side wall of the trench and a second part stretching horizontally along the surface of a substrate. A floating gate is arranged in the trench contiguously to the first part of the channel region while being isolated therefrom. A control gate is arranged on the second part of the channel region while being isolated therefrom. Side wall of the trench intersects the surface of the substrate at an acute angle to form a sharp edge. The second part of the channel region stretches from a second region toward the sharp edge and the floating gate to define a passage for programming the floating gate with electrons by high temperature electron injection. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2003303908A

公开(公告)日：2003-10-24

申请号：JP2003087103

申请日：2003-03-27

Applicant: Silicon Storage Technology Inc ,  シリコン ストーリッジ テクノロージー インコーポレイテッド

Inventor： YAU WEN FU ,  KIANIAN SOHRAB

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/105 ,  H01L27/11553

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligning method for forming a downsized memory cell having a novel structure, and to provide a memory cell array formed by using the same. SOLUTION: The method is for forming an array of floating gate memory cells, each provided with a trench formed in the surface of a semiconductor substrate and with the source and drain regions separated from each other with a channel region formed in between, and the array is formed by using this method. The source region is formed under the trench, and the channel region includes a part which extends along the trench sidewall and a second part horizontally, extending along the substrate surface. The conductive floating gate is positioned adjacent to the first part of the channel region in the trench and is insulated therefrom. The conductive control gate is positioned on the second part of the channel region and is insulated therefrom. The bottom of a conductive material block is positioned adjacent to the floating gate in the trench and is insulated therefrom. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种用于形成具有新颖结构的小型存储单元的自对准方法，并提供通过使用该存储单元阵列形成的存储单元阵列。 解决方案：该方法用于形成浮置栅极存储单元的阵列，每个浮置栅极存储单元设置有形成在半导体衬底的表面中的沟槽，并且源极和漏极区域彼此分离，沟道区域之间形成， 并且通过使用该方法形成阵列。 源极区域形成在沟槽下方，并且沟道区域包括沿着沟槽侧壁延伸的部分和沿着衬底表面水平延伸的第二部分。 导电浮栅位于沟槽中的沟道区的第一部分附近并与之绝缘。 导电控制栅极位于沟道区域的第二部分上并与其绝缘。 导电材料块的底部定位成与沟槽中的浮动栅极相邻并与其绝缘。 版权所有（C）2004，JPO

公开(公告)号：JP2021536600A

公开(公告)日：2021-12-27

申请号：JP2021509739

申请日：2019-07-09

Applicant: シリコン ストーリッジ テクノロージー インコーポレイテッド ,  SILICON STORAGE TECHNOLOGY, INC.

Inventor： トラン、ヒュー バン ,  ブー、サン ,  リ、アン ,  ホン、スタンレー

IPC: G11C16/04 ,  G11C11/54 ,  G06G7/60 ,  G06N3/063

Abstract: 深層学習ニューラルネットワークで使用するためのアナログニューロモーフィックメモリシステムについて、多数の実施形態が開示される。アナログニューロモーフィックメモリシステムは、複数のベクトルマトリックス乗算アレイと、それらのアレイによって共有される様々な構成要素とを備える。共有構成要素は、高電圧生成ブロック、検証ブロック、及び試験ブロックを含む。アナログニューロモーフィックメモリシステムは、長・短期メモリシステム又はゲート付き回帰型ユニットシステム内で任意選択的に使用される。 【選択図】図8