公开(公告)号：JP5491694B2

公开(公告)日：2014-05-14

申请号：JP2007308094

申请日：2007-11-28

申请人： スパンション エルエルシー

发明人： 文彦 井上 ,  貴之 丸山 ,  正幸 佐藤

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/743 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： The method for manufacturing the semiconductor device, which includes the steps of forming a charge storage layer (22) on a semiconductor substrate (10), forming an extending first groove (12) in the charge storage layer and the semiconductor substrate using a mask layer (30) formed on the charge storage layer as a mask, forming an insulating film (14) in the first groove, forming a second groove (32) extending across the first groove in the mask layer and the insulating film, forming a gate insulating film (18) formed below the second groove, forming a first conductive layer (34) in the second groove, eliminating the mask layer, forming a second conductive layer (36) on both side surfaces of the first conductive layer to form a word line (16) which includes the first and the second conductive layers, and eliminating the charge storage layer using the word line as a mask.

公开(公告)号：JP5281267B2

公开(公告)日：2013-09-04

申请号：JP2007274887

申请日：2007-10-23

申请人： ライジング シリコン,インコーポレイテッド

发明人： クロイプル フランツ

IPC分类号： H01L27/105 ,  H01L45/00 ,  H01L49/00

CPC分类号： H01L29/78 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  H01L29/0673 ,  H01L29/42324 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7887

摘要： The circuit has a gate oxide layer (308) arranged on a channel of a semiconductor-transistor. A changeable gate-stack-layer is arranged between the gate oxide layer and a gate electrode (312). The gate-stack (310) has a resistive switching element whose conductivity is changed for changing an on-resistance of the semiconductor-transistor. The transistor stores information based on changing of the on-resistance of the transistor at a preset gate-voltage. The gate-stack-layer is made of a phase-change material e.g. chalcogenide glass. Independent claims are also included for the following: (1) a method for producing an integrated circuit (2) a system comprising a processor (3) a hard disk drive mechanism comprising a controller (4) a method for storing information (5) a method for producing a memory cell.

公开(公告)号：JP5264139B2

公开(公告)日：2013-08-14

申请号：JP2007263502

申请日：2007-10-09

申请人： スパンション エルエルシー

发明人： 文彦 井上 ,  貴之 丸山

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： There is provided a method for manufacturing a flash memory device comprising forming a first insulating film and a conductive layer on a semiconductor substrate; forming a first mask layer on the conductive layer; forming a second mask layer in isolation regions isolated between the first mask layer,- forming first openings by removing the conductive layer and the first insulating film by using the first and second mask layer as a mask; forming a second insulating film in the first openings and the isolation regions; removing the first mask layer, the conductive layer and the first insulating film by using the second insulating film as a mask, forming gate electrodes between the second openings; removing, through the second openings, the first insulating film, forming a gate insulating film at center portions below the gate electrodes; and forming a charge storage layer in an area where the first insulating film is removed. The finished device' has bit lines (18), gate insulating film (22), tunnel insulating film (12), separated charge storage layer (14), top insulating film (12), and gate electrode (24).

公开(公告)号：JP5230870B2

公开(公告)日：2013-07-10

申请号：JP2008545894

申请日：2006-11-08

申请人： フリースケール セミコンダクター インコーポレイテッド

发明人： ティ． スウィフト、クレイグ ,  エル． チンダロール、ゴウリシャンカー ,  ビー． ダオ、トゥイ ,  エイ． サッド、マイケル

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

公开(公告)号：JP5069858B2

公开(公告)日：2012-11-07

申请号：JP2006000910

申请日：2006-01-05

申请人： 三星電子株式会社Samsung Electronics Co.,Ltd.

发明人： 東 勳 姜 ,  玩 濬 朴 ,  在 雄 玄 ,  元 柱 金 ,  禎 希 韓

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C11/56 ,  G11C2213/17 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/938 ,  Y10S977/943

摘要： A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.

公开(公告)号：JP2011066436A

公开(公告)日：2011-03-31

申请号：JP2010247676

申请日：2010-11-04

申请人： Micron Technology Inc ,  マイクロン テクノロジー、インコーポレイテッド

发明人： PRALL KIRK

IPC分类号： H01L29/792 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L29/7923

摘要： PROBLEM TO BE SOLVED: To provide a NAND type multi-state memory cell capable of achieving high memory density, low power consumption, and high reliability. SOLUTION: A NAND type multi-state memory cell has two drain/source regions on a substrate. At the upper part of the substrate between the two drain/source regions, an oxide-nitride-oxide structure is formed. The nitride layer acts as an asymmetric charge trapping layer. At the upper part of the oxide-nitride-oxide structure, a control gate is disposed. By applying an asymmetrical bias across the drain/source region, a high voltage is generated therein. Thereby, GIDL (Gate Induced Drain Leakage) hole injection processing is performed for the trapping layer substantially adjacent the drain/source region and holes are injected in an asymmetrical distribution. COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 要解决的问题：提供能够实现高存储密度，低功耗和高可靠性的NAND型多状态存储单元。 解决方案：NAND型多态存储单元在衬底上具有两个漏极/源极区域。 在两个漏极/源极区之间的衬底的上部，形成氧化物 - 氧化物 - 氧化物结构。 氮化物层用作不对称电荷捕获层。 在氧化物 - 氧化物 - 氧化物结构的上部设置有控制栅极。 通过在漏极/源极区域上施加不对称偏置，在其中产生高电压。 由此，对于基本上与漏极/源极区域相邻的捕获层进行GIDL（栅极引入漏极泄漏）空穴注入处理，并且以非对称分布注入空穴。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP4593088B2

公开(公告)日：2010-12-08

申请号：JP2003198259

申请日：2003-07-17

申请人： 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.

发明人： 裕 男 全 ,  永 善 兪 ,  成 基 朴 ,  溶 郁 金

IPC分类号： H01L21/8247 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L27/115 ,  H01L29/7887

摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating g ate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.

公开(公告)号：JP4557678B2

公开(公告)日：2010-10-06

申请号：JP2004314406

申请日：2004-10-28

申请人： イノテック株式会社

发明人： 高 三井田

IPC分类号： H01L21/8247 ,  G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L29/7887

摘要： A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

公开(公告)号：JP4472934B2

公开(公告)日：2010-06-02

申请号：JP2003036005

申请日：2003-02-14

申请人： イノテック株式会社

发明人： ▲高▼ 三井田

IPC分类号： G11C16/04 ,  H01L21/8247 ,  G11C16/02 ,  G11C16/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11524 ,  H01L27/11553 ,  H01L29/7887

摘要： A cell transistor (TC) includes source/drain regions (BL) formed at a lower level than part of its channel region. A select transistor (STE) has a channel region and source/drain regions formed at substantially the same level as the source/drain regions (BL) of the cell transistor (TC). One of the source/drain regions (BL) of the cell transistor (TC) and one of the source/drain regions of the select transistor (STE) are electrically interconnected to each other in substantially the same plane.

公开(公告)号：JP2010517306A

公开(公告)日：2010-05-20

申请号：JP2009547344

申请日：2008-01-10

申请人： フリースケール セミコンダクター インコーポレイテッド

发明人： ムラリダル，ラマチャンドラン ,  ラオ，ラジェッシュ・エイ

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7887

摘要： A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.