公开(公告)号：JP5543950B2

公开(公告)日：2014-07-09

申请号：JP2011206893

申请日：2011-09-22

申请人： 株式会社東芝

发明人： 充 佐藤 ,  恵 石月 ,  大 木藤 ,  篤史 今野 ,  良宏 阿久津 ,  傑 鬼頭 ,  嘉晃 福住 ,  竜太 勝又

IPC分类号： H01L27/115 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/265 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66833

摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

公开(公告)号：JP5383241B2

公开(公告)日：2014-01-08

申请号：JP2009032988

申请日：2009-02-16

申请人： 株式会社東芝

发明人： 竜太 勝又 ,  傑 鬼頭 ,  嘉晃 福住 ,  大 木藤 ,  啓安 田中 ,  陽介 小森 ,  恵 石月 ,  英明 青地

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

公开(公告)号：JP5380190B2

公开(公告)日：2014-01-08

申请号：JP2009169954

申请日：2009-07-21

申请人： 株式会社東芝

发明人： 友子 藤原 ,  竜太 勝又 ,  傑 鬼頭 ,  嘉晃 福住 ,  大 木藤 ,  啓安 田中 ,  陽介 小森 ,  恵 石月 ,  絢也 松並 ,  英明 青地 ,  亮平 桐澤 ,  義政 三ヶ尻 ,  繁人 大田

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.

公开(公告)号：JP5300419B2

公开(公告)日：2013-09-25

申请号：JP2008284375

申请日：2008-11-05

申请人： 株式会社東芝

发明人： 大 木藤 ,  竜太 勝又 ,  傑 鬼頭 ,  嘉晃 福住 ,  啓安 田中 ,  陽介 小森 ,  恵 石月 ,  英明 青地

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.

公开(公告)号：JP5269022B2

公开(公告)日：2013-08-21

申请号：JP2010212858

申请日：2010-09-22

申请人： 株式会社東芝

发明人： 竜太 勝又 ,  和幸 東 ,  嘉晃 福住

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.

公开(公告)号：JP5193551B2

公开(公告)日：2013-05-08

申请号：JP2007262244

申请日：2007-10-05

申请人： 株式会社東芝

发明人： 傑 鬼頭 ,  竜太 勝又 ,  嘉晃 福住 ,  大 木藤 ,  啓安 田中 ,  泰之 松岡 ,  英明 青地

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7923 ,  H01L29/7926

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.

公开(公告)号：JP5121869B2

公开(公告)日：2013-01-16

申请号：JP2010066706

申请日：2010-03-23

申请人： 株式会社東芝

发明人： 一郎 水島 ,  伸二 森 ,  嘉晃 福住 ,  史記 相宗

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.

公开(公告)号：JP5044624B2

公开(公告)日：2012-10-10

申请号：JP2009220985

申请日：2009-09-25

申请人： 株式会社東芝

发明人： 義政 三ヶ尻 ,  竜太 勝又 ,  繁人 大田 ,  陽介 小森 ,  大 木藤 ,  亮平 桐澤 ,  啓安 田中 ,  恵 石月 ,  嘉晃 福住 ,  友子 藤原 ,  英明 青地 ,  傑 鬼頭

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/34 ,  G11C5/02 ,  G11C16/26

摘要： A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.

公开(公告)号：JP4630747B2

公开(公告)日：2011-02-09

申请号：JP2005207628

申请日：2005-07-15

申请人： 株式会社東芝

发明人： 昌彦 中山 ,  達也 岸 ,  純夫 池川 ,  正 甲斐 ,  嘉晃 福住

IPC分类号： H01L43/08 ,  G11C11/15 ,  H01F10/08 ,  H01L21/8246 ,  H01L27/105

公开(公告)号：JP4406407B2

公开(公告)日：2010-01-27

申请号：JP2006067963

申请日：2006-03-13

申请人： 株式会社東芝

发明人： 正 甲斐 ,  嘉晃 福住

IPC分类号： H01L21/8246 ,  G11C11/15 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C11/16

摘要： A magnetic random access memory according to an embodiment of the present invention comprises first and second write lines which cross each other, and a magnetoresistive element whose center point is not overlapped onto a cross portion of the first and second write lines, wherein a center line of the magnetoresistive element in a direction of easy magnetization and center lines of the first and second write lines form a triangle.