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    Nonvolatile semiconductor memory device
    3.
    发明专利
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：JP2005064529A

    公开(公告)日：2005-03-10

    申请号：JP2004295635

    申请日：2004-10-08

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： KUZUHARA TAKESHI ,  IWAMORI NORIYUKI ,  NAKAYAMA YOSHIAKI ,  MIZUNO SHOJI ,  OHIRA SATOSHI

    IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing processes of a nonvolatile semiconductor memory device. SOLUTION: A control gate 5 is formed on a field insulating film 2. A floating gate 10 is then formed on the control gate 5 through an insulating film 7. The floating gate 10 is constituted so as to extend from the control gate 5 to on a first gate film 8a. Such structure allows a lower electrode 6 of a capacitor concurrently formed on a Si substrate 1 with the EPROM, and the control gate 5 to be formed, and the floating gate 10 to be concurrently formed with a top electrode 11 of the capacitor. Moreover, a gate oxide film 8b of a MOS transistor concurrently formed on the Si substrate 1 with the EPROM, and a first gate film 8a of EPROM are simultaneously formed. This allows manufacturing processes to be reduced. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 解决的问题：减少非易失性半导体存储器件的制造工艺。 解决方案：控制栅5形成在场绝缘膜2上。然后，通过绝缘膜7在控制栅5上形成浮栅10.浮栅10被构造成从控制栅延伸 5到第一栅极膜8a上。 这种结构允许同时形成在Si衬底1上的电容器的下电极6与EPROM，并且要形成控制栅极5，并且浮栅10与电容器的顶电极11同时形成。 此外，同时形成在Si衬底1上同时形成有EPROM的MOS晶体管的栅极氧化膜8b和EPROM的第一栅极膜8a。 这允许减少制造工艺。 版权所有（C）2005，JPO＆NCIPI

    Semiconductor device
    4.
    发明专利
    Semiconductor device 审中-公开

    公开(公告)号：JP2004039919A

    公开(公告)日：2004-02-05

    申请号：JP2002196003

    申请日：2002-07-04

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： MIZUNO SHOJI ,  NAKAYAMA YOSHIAKI ,  IWAMORI NORIYUKI

    IPC: H01L27/04 ,  H01L21/822

    Abstract: PROBLEM TO BE SOLVED: To prevent metal of a thin film resistor from causing an oxidization reaction and hereby being broken.
    SOLUTION: A CrSi film 22 is formed on a silicon substrate via an insulating film, and at opposite ends of which electrode patterns 24a, 24b are formed. A slit 23 is formed longitudinally at the center of the CrSi film 22. An aluminum electrode 25 is disposed via an insulating film on the CrSi film 22 so as to intersect an aluminum electrode 25. Even when a foreign substance P remains in a manufacturing process, and water invades, overall oxidization on the CrSi film 22 is prevented at the slit 23 to prolong the time until it reaches a broken state.
    COPYRIGHT: (C)2004,JPO

    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
    5.
    发明专利
    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2001060634A

    公开(公告)日：2001-03-06

    申请号：JP23417399

    申请日：1999-08-20

    Applicant: DENSO CORP

    Inventor： KONO KENJI ,  MIZUNO SHOJI

    IPC: H01L27/04 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To enable a semiconductor device to be lessened in number of processes and in manufacturing cost. SOLUTION: An up-drain MOSFET 8, an NPN transistor 9, and a double-well CMOS 10 are formed in a silicon 4 on a SOI substrate 1. A P-well region 50 and an N-well region 58 used in the double-well CMOS 10 are also formed in an up-drain MOSFET forming region and a bipolar transistor forming region respectively, and the up-drain MOSFET 8 and the NPN transistor 9 comprise P-well regions 13 and 31 and N-well regions 18 and 37, respectively.

    Method for inspecting insulated gate bipolar transistor
    6.
    发明专利
    Method for inspecting insulated gate bipolar transistor 有权
    检查绝缘栅双极晶体管的方法

    公开(公告)号：JP2009302462A

    公开(公告)日：2009-12-24

    申请号：JP2008158016

    申请日：2008-06-17

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： TOMATSU YUTAKA ,  MIZUNO SHOJI

    IPC: H01L21/336 ,  H01L29/739 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To achieve a method for inspecting an insulated gate bipolar transistor, capable of inspecting the intrinsic gettering performance efficiently and estructively. SOLUTION: The intrinsic gettering performance of an IGBT 1 is inspected by measuring the current amplification rate (HFE) of an PNP transistor 30 formed of a channel region 12, a drift layer 11, a buffer layer 17 and a collector layer 18. The current amplification rate (HFE) is measured while using an emitter electrode 16 of the IGBT 1 as a collector terminal C1 of the PNP transistor 30, an EQR (equipotential ring) 20 connected to the drift layer 11 of the IGBT 1 as a base terminal of the PNP transistor 30, and a collector electrode of the IGBT as an emitter terminal E1 of the PNP transistor 30. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：实现用于检查绝缘栅双极晶体管的方法，其能够有效地和破坏性地检查固有的吸杂性能。 解决方案：通过测量由沟道区12，漂移层11，缓冲层17和集电极层18形成的PNP晶体管30的电流放大率（HFE）来检查IGBT 1的固有吸杂性能 在使用IGBT1的发射电极16作为PNP晶体管30的集电极端子C1的同时测量电流放大率（HFE），连接到IGBT 1的漂移层11的EQR（等电位环）20作为 PNP晶体管30的基极端子和IGBT的集电极作为PNP晶体管30的发射极端子E1。（C）2010，JPO＆INPIT

    Driving circuit for transistor
    8.
    发明专利
    Driving circuit for transistor 有权
    驱动电路用于晶体管

    公开(公告)号：JP2008035068A

    公开(公告)日：2008-02-14

    申请号：JP2006204769

    申请日：2006-07-27

    Applicant: Denso Corp ,  Toyota Central Res & Dev Lab Inc ,  株式会社デンソー ,  株式会社豊田中央研究所

    Inventor： KUWABARA MAKOTO ,  HATSUTORI YOSHIKUNI ,  OKADA KYOKO ,  MIZUNO SHOJI ,  AOKI TAKAAKI ,  TAKAHASHI SHIGEKI ,  AKAGI NOZOMI ,  NAKANO TAKASHI

    IPC: H03K17/687 ,  H02M1/08

    Abstract: PROBLEM TO BE SOLVED: To break down a trade-off relation between a serge voltage and a turn-off loss existing in a transitional stage in which a transistor is turned off in a circuit for driving the transistor.
    SOLUTION: A driving circuit 10 is provided with an adjustment circuit 20 for adjusting the resistance value of the gate resistance of a transistor 30. An adjustment circuit 20 adjusts the resistance value of the gate resistance of the transistor gate 30 based on the current value of the negative gate currents Ig(-) of the transistor 30. Thus, the driving circuit 10 rapidly varies drain currents at the beginning of the transitional stage when the transistor 30 is turned off, and slowly varies the drain currents in the end of the transitional stage when the transistor 30 is turned off.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：分解在用于驱动晶体管的电路中晶体管截止的过渡阶段中存在的脉冲电压和关断损耗之间的权衡关系。 解决方案：驱动电路10设置有用于调整晶体管30的栅极电阻的电阻值的调整电路20.调节电路20基于该晶体管30的栅极电阻的电阻值调整晶体管栅极30的栅极电阻 晶体管30的负栅极电流Ig（ - ）的电流值。因此，当晶体管30截止时，驱动电路10在过渡阶段开始时迅速地改变漏极电流，并且最终缓慢地改变漏极电流 当晶体管30截止时，该过渡阶段。 版权所有（C）2008，JPO＆INPIT

    Switching circuit
    9.
    发明专利
    Switching circuit 审中-公开
    切换电路

    公开(公告)号：JP2007295543A

    公开(公告)日：2007-11-08

    申请号：JP2007073382

    申请日：2007-03-20

    Applicant: Denso Corp ,  Toyota Central Res & Dev Lab Inc ,  株式会社デンソー ,  株式会社豊田中央研究所

    Inventor： HATSUTORI YOSHIKUNI ,  KUWABARA MAKOTO ,  OKADA KYOKO ,  MIZUNO SHOJI ,  AOKI TAKAAKI

    IPC: H03K17/16 ,  H02M1/00 ,  H02M1/08 ,  H03K17/06 ,  H03K17/56 ,  H03K17/687

    Abstract: PROBLEM TO BE SOLVED: To provide a switching circuit capable of simultaneously suppressing both a switching loss and a surge voltage. SOLUTION: The present invention relates to a switching circuit for temporally switching main electrodes of a transistor between a conducted state and a non-conducted state by switching a gate voltage of the transistor, wherein a drain or a collector of the transistor and its gate or the drain or the collector of the transistor and its source or its emitter are connected by a series circuit of a Zener diode and a capacitor. While a drain voltage is low, a state is judged where capacitance of the capacitor is not contributed by the Zener diode, a drain current and the drain voltage vary at high speed, thereby reducing the switching loss. When the drain voltage increases, the Zener diode surrenders, the capacitance of the capacitor is added and the drain current and the drain voltage vary at a low speed, thereby suppressing the surge voltage low. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够同时抑制开关损耗和浪涌电压两者的开关电路。 解决方案：本发明涉及一种通过切换晶体管的栅极电压来暂时切换导通状态和非导通状态之间的晶体管的主电极的开关电路，其中晶体管的漏极或集电极和 其栅极或晶体管的漏极或集电极及其源极或发射极通过齐纳二极管和电容器的串联电路连接。 当漏极电压低时，判定电容器的电容不由齐纳二极管贡献的状态，漏极电流和漏极电压以高速变化，从而降低开关损耗。 当漏极电压增加时，齐纳二极管投降，电容器的电容被增加，漏极电流和漏极电压以低速度变化，从而抑制浪涌电压低。 版权所有（C）2008，JPO＆INPIT

    Semiconductor device
    10.
    发明专利
    Semiconductor device 有权
    半导体器件

    公开(公告)号：JP2012160706A

    公开(公告)日：2012-08-23

    申请号：JP2011271505

    申请日：2011-12-12

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： OSAWA SEIGO ,  TOMATSU YUTAKA ,  MIZUNO SHOJI

    IPC: H01L29/78 ,  H01L29/739

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining stable recovery dielectric strength.SOLUTION: A semiconductor chip 1 comprises an outer peripheral region 3 in the outer periphery of an element part 2. The element part 2 has contacts 26 electrically connecting with a semiconductor substrate 13 and a source electrode 24. In one surface 14 of the semiconductor substrate 13, the resistance value per unit area of an end portion 26a of each contact 26 at the outer peripheral region 3 side of the element part 2 is higher than that of a portion of each contact 26 at the element part 2 side. For this reason, since holes accumulated in the outer peripheral region 3 of the semiconductor chip 1 hardly flow into the end portions 26a of the contacts 26, the holes do not concentratively flow into the end portions 26a of the contacts 26 during recovery. This equalizes the flow of the holes from the outer peripheral region 3 to the contacts 26, thereby obtaining the stable recovery dielectric strength.

    Abstract translation: 要解决的问题：提供能够获得稳定的恢复绝缘强度的半导体器件。 解决方案：半导体芯片1包括在元件部分2的外周中的外周区域3.元件部件2具有与半导体基板13和源电极24电连接的触点26.在一个表面14中， 半导体基板13，元件部2的外周区域3侧的各触点26的端部26a的单位面积的电阻值高于元件部2侧的各触点26的部分的电阻值。 因此，由于在半导体芯片1的外周区域3中蓄积的孔几乎不流入触点26的端部26a，所以在恢复时孔不会集中地流入触点26的端部26a。 这使得从外周区域3到触点26的孔的流动相等，从而获得稳定的恢复绝缘强度。 版权所有（C）2012，JPO＆INPIT

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