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    不揮発性半導体記憶装置及びその動作方法
    4.
    发明专利
    不揮発性半導体記憶装置及びその動作方法 审中-公开
    非易失性半导体存储器件及其操作方法

    公开(公告)号：JP2014241180A

    公开(公告)日：2014-12-25

    申请号：JP2013122943

    申请日：2013-06-11

    Applicant: 株式会社東芝 ,  Toshiba Corp

    Inventor： YASUDA NAOKI ,  FUKUZUMI YOSHIAKI

    IPC: G11C16/02 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/0483 ,  G11C16/16 ,  G11C16/3454

    Abstract: 【課題】メモリセルの劣化を抑制することのできる不揮発性半導体記憶装置を提供する。【解決手段】一の実施の形態に係る不揮発性半導体記憶装置は、電気的書き換え可能な複数のメモリトランジスタが配列されたメモリセルアレイと、選択メモリトランジスタに所定の印加電圧を印加して選択メモリトランジスタが導通する閾値電圧を変化させる電圧印加動作、及び選択メモリトランジスタの閾値電圧が所望の値に変化しなかった場合に印加電圧を所定のステップアップ値だけ上昇させるステップアップ動作を繰り返す制御を司る制御部とを備える。制御部は、電圧印加動作の回数が増えるにつれステップアップ値を単調に減少させるようにステップアップ動作を制御する。【選択図】図7

    Abstract translation: 要解决的问题：提供一种能够抑制存储单元劣化的非易失性半导体存储装置。解决方案：根据一个实施例的非易失性半导体存储装置包括：布置有多个电可重写存储晶体管的存储单元阵列; 以及控制器，执行控制以重复施加电压的操作，以将预定的施加电压施加到所选择的存储晶体管，以改变用于使所选存储晶体管连续的阈值电压，以及用于将施加电压增加预定步骤的升压操作 如果所选择的存储晶体管的阈值电压不变为期望值，则为上限值。 控制器控制升压操作，以随着电压施加操作次数的增加而单调减小升压值。

    Non-volatile semiconductor memory device
    6.
    发明专利
    Non-volatile semiconductor memory device 有权

    公开(公告)号：JP5524140B2

    公开(公告)日：2014-06-18

    申请号：JP2011158565

    申请日：2011-07-20

    Applicant: 株式会社東芝

    Inventor： 斎 岩井 ,  友子 藤原 ,  傑 鬼頭 ,  英明 青地

    IPC: G11C16/02 ,  G11C16/04

    CPC classification number: G11C16/3454 ,  G11C16/0483 ,  G11C16/06

    Abstract: A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

    Power-on detection system for memory device
    7.
    发明专利
    Power-on detection system for memory device 有权
    用于存储器件的上电检测系统

    公开(公告)号：JP2014089796A

    公开(公告)日：2014-05-15

    申请号：JP2014002541

    申请日：2014-01-09

    Applicant: Sidense Corp ,  シデンス・コーポレーション

    Inventor： WLODEK KURJANOWICZ

    IPC: G11C16/06 ,  G11C16/02 ,  G11C17/14

    CPC classification number: G11C29/52 ,  G11C5/143 ,  G11C16/3454 ,  G11C16/3459 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C19/00 ,  G11C29/027 ,  G11C2029/0407

    Abstract: PROBLEM TO BE SOLVED: To provide a power-on detection system for a memory device.SOLUTION: A master latch circuit 310 and a slave latch circuit 312 of a dual function data register 310 can save words of two different pieces of data simultaneously. In a program verification operation, the master latch saves program data and the slave latch receives and saves read data. Comparison logic of each resister state compares data of both the latches with each other and integrates a comparison result with a comparison result of a precedent register stage. A result of final one bit indicates presence of at least one bit which is not programmed. At a logical level of a low or high active state of a clock signal, a shit operation is selectively started so as to output any of data words successively according to the clock.

    Abstract translation: 要解决的问题：提供用于存储器件的上电检测系统。解决方案：双功能数据寄存器310的主锁存电路310和从锁存电路312可以同时保存两个不同数据片段的字。 在程序验证操作中，主锁存器保存程序数据，从锁存器接收并保存读数据。 每个电阻状态的比较逻辑将两个锁存器的数据彼此进行比较，并将比较结果与先前的寄存器级的比较结果进行比较。 最后一位的结果表示存在至少一个未被编程的位。 在时钟信号的低或高有效状态的逻辑电平下，有选择地启动杂音操作，以便根据时钟连续地输出数据字。

    Non-volatile semiconductor memory and voltage trimming method for the same
    8.
    发明专利
    Non-volatile semiconductor memory and voltage trimming method for the same 审中-公开
    非挥发性半导体存储器及其相同的电压调制方法

    公开(公告)号：JP2014035776A

    公开(公告)日：2014-02-24

    申请号：JP2012176541

    申请日：2012-08-08

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： FUJIMURA SUSUMU

    IPC: G11C16/06 ,  G11C16/02 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3454

    Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable non-volatile semiconductor memory.SOLUTION: A non-volatile semiconductor memory includes: a plurality of blocks each of which has a plurality of memory cells; a plurality of bit lines; a plurality of sense amplifier circuits each of which has a first transistor; a plurality of second transistors arranged at positions close to the sense amplifier circuits of the plurality of bit lines, and connected to each of the plurality of bit lines; a plurality of third transistors arranged at positions far from the sense amplifier circuits of the plurality of bit lines, and connected to each of the plurality of bit lines; a source line; and a control circuit. The control circuit changes a voltage to be applied to the control line of the plurality of first transistors on the basis of a trimming voltage by which currents flowing in the control line to the plurality of second transistors and the plurality of third transistors are made the same when a first voltage is applied to the bit lines in accordance with the position of the selected block in which the plurality of selected memory cells are arranged.

    Abstract translation: 要解决的问题：提供高度可靠的非易失性半导体存储器。解决方案：非易失性半导体存储器包括：多个块，每个块具有多个存储单元; 多个位线; 多个读出放大器电路，每个都具有第一晶体管; 多个第二晶体管，布置在靠近所述多个位线的读出放大器电路的位置，并连接到所述多个位线中的每一个; 多个第三晶体管，其布置在远离所述多个位线的读出放大器电路的位置，并连接到所述多个位线中的每一个; 源线; 和控制电路。 控制电路基于修整电压来改变施加到多个第一晶体管的控制线的电压，通过该微调电压使得控制线中流向多个第二晶体管和多个第三晶体管的电流相同 当根据其中布置多个所选择的存储单元的所选块的位置向位线施加第一电压时。

    Semiconductor memory, system and method of operation of the semiconductor memory
    10.
    发明专利
    Semiconductor memory, system and method of operation of the semiconductor memory 有权

    公开(公告)号：JP5316299B2

    公开(公告)日：2013-10-16

    申请号：JP2009184386

    申请日：2009-08-07

    Applicant: 富士通セミコンダクター株式会社

    Inventor： 研吾 田仲 ,  修 飯岡

    IPC: G11C16/02 ,  G11C16/06

    CPC classification number: G11C16/3459 ,  G11C16/3454

    Abstract: A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a value being checked in the verify operation; a voltage generating circuit that generates a normal program voltage and a verify voltage based on the normal program signal and the verify signal and generates a soft program voltage based on the soft program signal; and a determination circuit that detects a pass when the threshold voltage reaches the value and detects the fail when the threshold voltage does not reach the value.

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