公开(公告)号：KR1020090115136A

公开(公告)日：2009-11-04

申请号：KR1020097016182

申请日：2008-01-23

Applicant: 엔엑스피 유에스에이, 인코포레이티드

Inventor： 팜,팀,브이. ,  우엘링,트렌트,에스.

IPC: H01L21/60 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract translation: 提供一种半导体器件，其包括具有设置在其上的多个接合焊盘（503）的衬底（501）。 每个接合焊盘在平行于基板的方向上具有长轴和短轴，并且长轴与短轴的比率随着焊盘与基板中心的距离而增加。

公开(公告)号：KR1020090108954A

公开(公告)日：2009-10-19

申请号：KR1020080034318

申请日：2008-04-14

Applicant: 삼성전자주식회사

Inventor： 한성찬 ,  양진규 ,  이동춘 ,  천광호

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H05K1/112 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10666 ,  H05K2203/0455 ,  Y02P70/613

Abstract: PURPOSE: A semiconductor package is provided to reduce the damage of the solder ball caused by the external shock. CONSTITUTION: A semiconductor package includes substrates(110,120) and a connection terminal(130). The substrate has socket portions. The connection terminals have the solder ball and the supporting part. The solder ball is located on the top of the substrate. The supporting part supports the solder ball by being inserted into the socket portion and extended from the solder ball. The socket portion includes a depression or a hole. The depression is defined by the side wall and the bottom part. The hole passes through the substrate. The substrate is the multilayer board in which the insulating layer and the inner wire are repeated or the printed circuit board which has the inner wire.

Abstract translation: 目的：提供半导体封装，以减少由外部冲击引起的焊球的损坏。 构成：半导体封装包括衬底（110,120）和连接端子（130）。 基板具有插座部分。 连接端子具有焊球和支撑部。 焊球位于基板的顶部。 支撑部分通过插入插座部分并从焊球延伸来支撑焊球。 插座部分包括凹陷或孔。 凹陷由侧壁和底部限定。 孔穿过衬底。 衬底是重复绝缘层和内部电线的多层板或具有内部电线的印刷电路板。

公开(公告)号：KR1020090105780A

公开(公告)日：2009-10-07

申请号：KR1020080076989

申请日：2008-08-06

Applicant: 삼성전기주식회사

Inventor： 박호식 ,  손경진 ,  신준식 ,  이상엽 ,  류정걸 ,  박정환 ,  목지수

IPC: H05K3/40

CPC classification number: H05K3/4007 ,  H05K3/0026 ,  H05K3/0041 ,  H05K3/3436 ,  H05K2201/10659

Abstract: PURPOSE: A printed circuit board and a manufacturing method thereof are provided to reduce thermal expansion coefficient of the printed circuit board by protecting an external circuit using the material with low thermal expansion coefficient. CONSTITUTION: A first resin layer with a first pattern is provided(S110). A conductive bump electrically connected to the first pattern is formed in one side of the first resin layer(S120). An insulation layer and the first resin layer are pressed to be penetrated by the conductive bump(S130). A second resin layer with a second pattern is stacked on the insulation layer(S140). An opening is formed by etching one of the first resin layer and the second resin layer(S150).

Abstract translation: 目的：提供印刷电路板及其制造方法，以通过使用具有低热膨胀系数的材料保护外部电路来降低印刷电路板的热膨胀系数。 构成：提供具有第一图案的第一树脂层（S110）。 电连接到第一图案的导电凸块形成在第一树脂层的一侧（S120）中。 绝缘层和第一树脂层被压接以被导电凸块穿透（S130）。 具有第二图案的第二树脂层层叠在绝缘层上（S140）。 通过蚀刻第一树脂层和第二树脂层中的一个形成开口（S150）。

公开(公告)号：KR1020090078417A

公开(公告)日：2009-07-20

申请号：KR1020080004236

申请日：2008-01-15

Applicant: (주) 디시티

Inventor： 권용태 ,  송정규 ,  이광학

IPC: H05K3/34 ,  H01L21/60 ,  H01L23/48

CPC classification number: H05K3/3436 ,  H01L23/488 ,  H05K3/3457 ,  H05K2201/10734 ,  H05K2203/0435

Abstract: A method for reballing a ball grid array is provided to prevent the damage of falling ball pad and scratch. A reballing subject is extracted among plurality of BGA (ball grid array) having a solder ball(11). The BGA is equipped on BGA fixation jig(2) having an inserting groove to install BGA and the solder ball is melted by heating BGA fixation jig. The melted solder ball is removed by spraying air having high pressure.

Abstract translation: 提供了一种球栅阵列重球的方法，以防止落球垫损伤和划伤。 在具有焊球（11）的多个BGA（球栅阵列）中提取重球主体。 BGA配备有具有插入槽的BGA固定夹具（2）以安装BGA，并且通过加热BGA固定夹具来熔化焊球。 通过喷射高压空气来去除熔化的焊球。

公开(公告)号：KR1020090051059A

公开(公告)日：2009-05-20

申请号：KR1020097004020

申请日：2007-09-06

Applicant: 파나소닉 주식회사

Inventor： 오카모토카주오 ,  니시쇼이치 ,  모리타타케시 ,  히요시마사노리 ,  토모야수카주히코

IPC: H05K13/04 ,  H05K13/08 ,  H05K3/34 ,  H05K13/02

CPC classification number: H05K3/3484 ,  H01L2224/81 ,  H05K3/1216 ,  H05K3/3436 ,  H05K2201/035 ,  H05K2201/10734 ,  H05K2203/0338 ,  H05K2203/163 ,  Y02P70/613

Abstract: 전극에 인쇄된 땜납 페이스트의 높이를 계측하는 높이 계측장치와 전자부품 탑재장치를 구비한 실장 시스템에 있어서, 전극에 인쇄된 땜납 페이스트의 높이를 계측한 계측결과에 기초하여 땜납 페이스트의 높이가 정상인지 아닌지를 판정하고, 또한 이 판정결과에 기초하여 땜납 범프로의 땜납 페이스트의 전사의 요부를 판정하고 전사 필요로 판정되었다면 탑재헤드에 유지된 전자부품에 페이스트를 전사한다. 이것에 의해, 인쇄불량에 기인하는 땜납량의 부족이 생긴 기판을 대상으로 하는 경우에 있어서 땜납량의 적정에 추가하여 실장 품질을 확보할 수 있다.

公开(公告)号：KR1020090042753A

公开(公告)日：2009-04-30

申请号：KR1020087016360

申请日：2008-04-02

Applicant: 이비덴 가부시키가이샤

Inventor： 가와노슈이치

IPC: H01L23/12 ,  H01L23/32

CPC classification number: H05K1/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/423 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/0733 ,  H01L2924/00

Abstract: An interposer (10) is provided with a substrate main body (12) having first and second through holes (14, 16); a capacitor (20) wherein a dielectric layer (24) and a second electrode section (26) are laminated on a first electrode section (22) formed on inner surfaces of the first and the second through holes (14, 16) and on a first surface of the substrate main body (12); an insulating layer (18) formed by filling a space, which is formed by being surrounded by the second electrode section (26) in the first through hole (14), with an electrical insulating material; and a first post (40) which penetrates the insulating layer (18), has one end electrically connected to the first electrode section (22) and is electrically insulated from the second electrode section (26). At the both ends of the first post (40), a first pad (31) and a second pad (32) are arranged, respectively. In the second through hole (16), a second post, which has the outer circumference surface connected to the second electrode section (26) and is electrically insulated from the first electrode section (22), is arranged. On the both ends of the second post (42), a third pad (33) and a fourth pad (34) are arranged, respectively.

Abstract translation: 插入件（10）设置有具有第一和第二通孔（14,16）的基板主体（12）。 电容器（20），其中在形成在第一和第二通孔（14,16）的内表面上的第一电极部分（22）上层压电介质层（24）和第二电极部分（26） 基板主体（12）的第一表面; 通过填充由第一通孔（14）中的第二电极部分（26）包围的空间形成的绝缘层（18），用电绝缘材料形成; 和穿过绝缘层（18）的第一柱（40），其一端电连接到第一电极部分（22）并与第二电极部分（26）电绝缘。 在第一柱（40）的两端分别布置有第一垫（31）和第二垫（32）。 在第二通孔（16）中，布置有与第二电极部分（26）连接并与第一电极部分（22）电绝缘的外周表面的第二柱体。 在第二柱（42）的两端分别布置有第三垫（33）和第四垫（34）。

公开(公告)号：KR1020090026891A

公开(公告)日：2009-03-16

申请号：KR1020070091955

申请日：2007-09-11

Applicant: 삼성전자주식회사

Inventor： 정예정 ,  김동한

IPC: H05K1/02 ,  H01L23/12

CPC classification number: H05K1/111 ,  H01L23/4985 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H05K1/189 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09709 ,  H05K2201/10674 ,  H05K2201/10681 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A wiring substrate, a tape package having the same, a display device having the same, a method of manufacturing the same, a method of manufacturing the tape package having the same and a method of manufacturing the display device having the same are provided to finely arranging the wirings by preventing the short circuit between the wirings. A wiring board(100) comprises a base film(110), a plurality of wiring(120), and an insulating member(130). A chip mounting range(112) is formed in the central part of the base film. The semiconductor chip comprises the central part and the peripheral part. An input pad and an output pad comprise the bumps for the electrical contact with wirings formed in the base film An input wire(122) electrically connects the semiconductor chip which is mounted in the chip mounting range and the printed circuit board. An output line(124) electrically connects the semiconductor chip and the display panel. The wirings comprises a junction end(125) welded to the bump of the semiconductor chip. The insulating member comprises the first insulating member(132) and the second insulating member(134).

Abstract translation: 布线基板，具有该布线基板的带包装，具有该布线基板的显示装置，其制造方法，具有该布线基板的带封装的制造方法以及具有该布带基板的显示装置的制造方法 通过防止布线之间的短路来布置布线。 布线板（100）包括基膜（110），多个布线（120）和绝缘构件（130）。 芯片安装范围（112）形成在基膜的中心部分。 半导体芯片包括中心部分和周边部分。 输入焊盘和输出焊盘包括用于与形成在基膜中的布线的电接触的凸块。输入线（122）将安装在芯片安装范围内的半导体芯片与印刷电路板电连接。 输出线（124）电连接半导体芯片和显示面板。 所述布线包括焊接到所述半导体芯片的凸起的接合端（125）。 绝缘构件包括第一绝缘构件（132）和第二绝缘构件（134）。

公开(公告)号：KR1020080089374A

公开(公告)日：2008-10-06

申请号：KR1020087015967

申请日：2006-12-21

Applicant: 마이크론 테크놀로지, 인크.

Inventor： 킨슬리,토마스

IPC: G01R31/307 ,  G01R31/28

CPC classification number: B23K1/0016 ,  G01R31/048 ,  H05K1/0268 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/10734 ,  H05K2203/163 ,  H05K2203/175 ,  Y02P70/611 ,  Y10T29/49004 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: Embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed.

Abstract translation: 本发明的实施例一般涉及测试存储器件与电路板或其他器件的连接。 在一个实施例中，公开了一种被配置为便于该设备与印刷电路板或其他设备之间的连续性测试的存储器件。 存储器件包括一个基片和两个通过测试路径彼此电耦合的连接焊盘。 还公开了一种用于测试存储器件和电路板或其它器件之间的连接的系统和方法。

公开(公告)号：KR1020080083127A

公开(公告)日：2008-09-16

申请号：KR1020087016020

申请日：2006-12-11

Applicant: 인텔 코포레이션

Inventor： 최,희만 ,  서,대웅

IPC: B23K35/40 ,  H05K3/34 ,  B23K35/22

CPC classification number: B23K35/025 ,  B23K35/22 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0116 ,  H05K2201/0308 ,  Y02P70/613 ,  Y10S428/929 ,  Y10T428/12181 ,  Y10T428/12479

Abstract: A foamed solder or a nano-porous solder is formed on a substrate of an integrated circuit package. The foamed solder exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed solder is used as a solder bump for communication between an integrated circuit device and external structures.

Abstract translation: 在集成电路封装的基板上形成发泡焊料或纳米多孔焊料。 泡沫焊料表现出低的模量，抗冲击和动态载荷下的开裂。 泡沫焊料用作集成电路器件和外部结构之间的通信的焊料凸块。

公开(公告)号：KR100841138B1

公开(公告)日：2008-06-24

申请号：KR1020057018602

申请日：2004-02-06

Applicant: 인텔 코포레이션

Inventor： 후아,페이

IPC: B23K35/26 ,  C22C13/00

CPC classification number: H01L24/10 ,  B23K35/262 ,  B23K2201/42 ,  H01L24/13 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01063 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2924/00 ,  H01L2224/05599

Abstract: 중량비 85-96 wt.% 주석(Sn)과 4-15 wt.% 인듐(In)을 포함하는 무연 솔더와 그 예시적 사용이 개시되어 있다. Sn-In 솔더는 리플로우(reflow) 온도로부터 실내 온도까지 냉각될 때 마르텐사이트계 상 변화를 겪는다. 결과로서, 접합된 구성 요소들 사이에서 상대적 이동에 의해 야기된 솔더 변형에 의해 일반적으로 발생한 잔여 응력이 실제로 감소된다. 통상적으로, 상대적인 이동은 접합된 구성 요소들 사이에서 열팽창 계수(CTE)의 불일치에 기인한다. 개시된 예시적인 사용은 플립-칩 어셈블리와, BGA 패키지와 같은, 회로 기판에 탑재된 IC 패키지를 포함한다.
무연 솔더, 마르텐사이트, 리플로우, 상변화, 초소성