公开(公告)号：KR20070077693A

公开(公告)日：2007-07-27

申请号：KR20060007411

申请日：2006-01-24

申请人： HYNIX SEMICONDUCTOR INC

发明人： SEO JAE WOOK ,  LEE CHUL SEUNG ,  HONG SUNG MOK

IPC分类号： H01L21/027

CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/54426

摘要： An overlay vernier and a method of fabricating a semiconductor device using the same are provided to enable one overlay vernier to have various space line widths and pitches by forming the overlay vernier having space patterns of right-angled triangle shape. An overlay vernier includes an outer box and an inner box(120). The outer box is formed by arranging four space patterns of a right-angled triangle shape on four sides of a rectangular pattern. The inner box is formed in a center portion of the outer box. The space patterns are arranged along a longitudinal axis of the rectangular pattern.

摘要翻译： 提供一种覆盖游标和制造使用其的半导体器件的方法，以通过形成具有直角三角形形状的空间图案的覆盖游标，使得一个覆盖游标具有各种空间线宽度和间距。 覆盖游标包括外盒和内箱（120）。 外箱通过在矩形图案的四边上布置四个直角三角形的空间图案而形成。 内箱形成在外箱的中心部分。 空间图案沿着矩形图案的纵向轴线布置。

公开(公告)号：KR20070077692A

公开(公告)日：2007-07-27

申请号：KR20060007410

申请日：2006-01-24

申请人： HYNIX SEMICONDUCTOR INC

发明人： JUN HYUN SOOK

IPC分类号： H01L21/027

CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/54426

摘要： An overlay vernier and a method for measuring an overlay using the same are provided to amplify a signal of a stepped portion of an overlay vernier by forming a basic material on the stepped portion and coating it by fluorescein. An overlay vernier includes a basic substance(140) buried in stepped portions of the overlay vernier and fluorescein coated on the basic material. The overlay vernier is formed on a margin area of a semiconductor substrate, and then the stepped portion is buried by the basic substance. The basic material is coated by the fluorescein, and a light emitting portion is irradiated by light to measure a wavelength of the reflected light.

摘要翻译： 提供覆盖游标和使用其的测量覆盖层的方法，以通过在阶梯部分上形成基底材料并用荧光素涂覆来叠放覆盖游标的阶梯部分的信号。 覆盖游标包括埋在覆盖游标的阶梯部分中的碱性物质（140）和涂覆在基础材料上的荧光素。 覆盖游标形成在半导体衬底的边缘区域上，然后阶梯部分被碱性物质掩埋。 基本材料被荧光素包被，并且用光照射发光部分以测量反射光的波长。

公开(公告)号：KR1020070076452A

公开(公告)日：2007-07-24

申请号：KR1020070003581

申请日：2007-01-12

申请人： 소니 주식회사

发明人： 이께베노부아끼 ,  이와후찌도시아끼 ,  사또오미찌히로 ,  야마가따유우지

IPC分类号： H01L21/66

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L24/26 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/0269 ,  H05K3/3436 ,  H05K2201/2054 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device, and a method and apparatus for testing the same are provided to precisely non-destructive inspect a gap between a substrate and a semiconductor chip in the semiconductor device. A semiconductor device includes a substrate(2), a semiconductor chip(3) mounted on the substrate and electrically connected to the substrate via a boss electrode(6), a first resin material filled in a gap between the substrate and the semiconductor chip, and a second resin material sealing the semiconductor chip mounted on the substrate. A first reflector for reflecting inspection light is formed on a surface of the substrate which faces the semiconductor chip. A second reflector for reflecting the inspection light is formed on the semiconductor chip which faces the substrate.

摘要翻译： 提供半导体器件及其测试方法和装置，以精确地无损检查半导体器件中的衬底和半导体芯片之间的间隙。 一种半导体器件，包括：衬底（2），安装在衬底上并通过凸台电极（6）电连接到衬底的半导体芯片（3）;填充在衬底和半导体芯片之间的间隙中的第一树脂材料， 以及密封安装在基板上的半导体芯片的第二树脂材料。 用于反射检查光的第一反射器形成在面向半导体芯片的基板的表面上。 用于反射检查光的第二反射器形成在面向基板的半导体芯片上。

公开(公告)号：KR1020070070538A

公开(公告)日：2007-07-04

申请号：KR1020050133180

申请日：2005-12-29

申请人： 동부일렉트로닉스 주식회사

发明人： 임수

IPC分类号： H01L27/146

CPC分类号： H01L27/14647 ,  H01L23/544 ,  H01L27/14698 ,  H01L2223/54426

摘要： A vertical CMOS image sensor and its manufacturing method are provided to define a gettering part without masking process by forming a pattern for defining the gettering part except an alignment pattern to a zero-mask required for alignment without using an additional mask, so that the productivity can be improved by implementing the gettering part through a simplified process. A pixel array region and a dummy area are formed on a silicon substrate(101). A first and a second epi layer(104,107) are formed sequentially on the entire surface of the silicon substrate. A first photodiode(103) is formed on the pixel array area of the silicon substrate. A second and a third photo diodes(106,108) are formed on the first and the second epi layer respectively by overlapping with a region of the first photodiode formation region. A first gettering part(102) is formed on a lower portion of a groove. A second gettering part(105) is formed on the first epi region corresponding to the around of the groove. A third gettering part(109) is formed on the second epi region corresponding to the upper portion of the groove.

摘要翻译： 提供垂直CMOS图像传感器及其制造方法以通过形成用于将除了对准图案之外的吸气部件定义为在不使用附加掩模的情况下进行对准所需的零掩模的图案来定义吸气部件而不进行掩模处理，从而生产率 可以通过简化的过程实现吸气部件来改进。 在硅衬底（101）上形成像素阵列区域和虚拟区域。 在硅衬底的整个表面上依次形成第一和第二外延层（104,107）。 第一光电二极管（103）形成在硅衬底的像素阵列区域上。 通过与第一光电二极管形成区域的区域重叠，分别在第一和第二外延层上形成第二和第三光电二极管（106,108）。 第一吸气部（102）形成在槽的下部。 第二吸气部（105）形成在对应于槽周围的第一外延区域上。 第三吸气部（109）形成在与槽的上部对应的第二外延区域上。

公开(公告)号：KR100734325B1

公开(公告)日：2007-06-26

申请号：KR20060066197

申请日：2006-07-14

申请人： SAMSUNG ELECTRONICS CO LTD

发明人： KIM YOUNG MOK

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76224 ,  H01L21/823878 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device is provided to reduce an expensive photolithography procedure for use in forming an align key by commonly using a photoresist pattern. A protective layer(110) is formed on a semiconductor substrate(100). A sacrificial layer(120) is formed on the protective layer. The sacrificial layer has etching selectivity with respect to the protective layer. A part of the sacrificial layer is selectively etched to form an align key(140). An aligned well(220) is formed on the semiconductor substrate by using the align key. An aligned isolation layer is formed on the semiconductor substrate where the well is formed by using the align key. Before the protective layer is formed, a different disaligned well(210) is formed on the semiconductor substrate. The different well surrounds the well.

摘要翻译： 提供一种用于制造半导体器件的方法，以通过通常使用光致抗蚀剂图案来减少用于形成对准键的昂贵的光刻步骤。 在半导体衬底（100）上形成保护层（110）。 在保护层上形成牺牲层（120）。 牺牲层相对于保护层具有蚀刻选择性。 牺牲层的一部分被选择性地蚀刻以形成对准键（140）。 通过使用对准键在半导体衬底上形成对准的阱（220）。 在半导体衬底上形成对准的隔离层，其中通过使用对准键形成阱。 在保护层形成之前，在半导体衬底上形成不同的对准阱（210）。 井不同的井。

公开(公告)号：KR1020070025027A

公开(公告)日：2007-03-08

申请号：KR1020050080753

申请日：2005-08-31

申请人： 에스케이하이닉스 주식회사

发明人： 황영선

IPC分类号： H01L21/027

CPC分类号： G03F9/708 ,  G03F7/70633 ,  H01L23/544 ,  H01L2223/54426

摘要： A method for manufacturing a semiconductor device is provided to prevent damage of a semiconductor substrate due to an etching and to increase accuracy of overlay by forming an oxide layer before forming a poly silicon layer when an overlay aligning mark is formed. A pad oxide layer and a pad nitride layer are formed on an upper portion of a semiconductor substrate(100). An isolation region is etched to form a first trench. An HDP(High Density Plasma) oxide layer(130) gap-filling the first trench is formed. An isolation layer is formed by performing a planarization etching process to expose the pad nitride layer. The isolation layer is etched in a predetermined depth by the whole surface etching process to form a second trench. The pad oxide layer and the pad nitride layer are removed. An oxide layer(140) and a poly silicon layer(150) are formed on an upper portion of the second trench and the upper portion of the semiconductor substrate. The poly silicon layer is etched by a recess gate region formation process to form an overlay aligning mark where a step of the second trench is remained.

摘要翻译： 提供一种制造半导体器件的方法，以防止由于蚀刻而导致的半导体衬底的损坏，并且当形成覆盖对准标记时，在形成多晶硅层之前通过形成氧化物层来提高覆盖精度。 衬底氧化物层和衬垫氮化物层形成在半导体衬底（100）的上部。 蚀刻隔离区以形成第一沟槽。 形成间隙填充第一沟槽的HDP（高密度等离子体）氧化物层（130）。 通过执行平坦化蚀刻工艺以暴露衬垫氮化物层来形成隔离层。 通过整个表面蚀刻工艺以预定的深度蚀刻隔离层以形成第二沟槽。 去除衬垫氧化物层和衬垫氮化物层。 在第二沟槽的上部和半导体衬底的上部形成氧化物层（140）和多晶硅层（150）。 通过凹陷栅区形成工艺蚀刻多晶硅层，形成覆盖对准标记，其中残留有第二沟槽的台阶。

公开(公告)号：KR100671805B1

公开(公告)日：2007-01-19

申请号：KR1020010061458

申请日：2001-10-05

申请人： 후지쯔 가부시끼가이샤

发明人： 와타나베겐이치

IPC分类号： H01L21/3205

CPC分类号： H01L21/76808 ,  H01L21/76838 ,  H01L23/5258 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： 다마신(damascene) 공정으로 작성하기에 적당한 신규한 다층 배선 구조를 갖는 반도체 장치를 제공한다.
반도체 장치는 복수의 반도체 소자를 갖는 반도체 기판 상에 형성되며 하층 다마신 배선을 갖는 제 1 절연층과, 그 위에 형성되며 제 2 다마신 배선과 제 1 단차를 형성하는 위치 맞춤 배선 패턴을 갖는 제 2 절연층과, 동일 표면 배선층으로 형성되며 제 2 다마신 배선을 덮는 표면 배선 패턴과 위치 맞춤 배선 패턴 위에 형성되며 제 1 단차를 반영하는 제 2 단차를 갖는 제 1 위치 맞춤 표면 배선 패턴과, 표면 배선 패턴과 제 1 위치 맞춤 표면 배선 패턴을 덮어서 제 2 절연층 상에 형성된 제 3 절연층을 갖는다.
위치 맞춤, 배선 패턴, 마커, 비어홀, 에칭 스토퍼층

摘要翻译： 提供了一种具有适合于通过镶嵌工艺制造的新型多层互连结构的半导体器件。

公开(公告)号：KR1020070003057A

公开(公告)日：2007-01-05

申请号：KR1020050058786

申请日：2005-06-30

申请人： 에스케이하이닉스 주식회사

发明人： 김우진 ,  오훈정

IPC分类号： H01L21/027 ,  H01L21/3063

CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/54426

摘要： A method of manufacturing an overlay key is provided to simplify manufacturing processes and to reduce fabrication costs by performing in-situ processing using a photoresist pattern for opening an overlay key region. A shallow trench isolation layer(18) is formed in a semiconductor substrate(10). A photoresist pattern for opening an overlay key region of the substrate is formed thereon. An overlay key pattern is formed on the resultant structure by recessing the shallow trench isolation layer of the overlay key region using a wet etching process. The photoresist pattern is removed from the resultant structure by using in-situ processing. Then, an in-situ cleaning process is performed on the resultant structure.

摘要翻译： 提供了制造覆盖键的方法，以简化制造工艺并通过使用光致抗蚀剂图案进行原位处理来打开覆盖键区域来降低制造成本。 在半导体衬底（10）中形成浅沟槽隔离层（18）。 在其上形成用于打开衬底的覆盖键区域的光致抗蚀剂图案。 通过使用湿蚀刻工艺使覆盖键区域的浅沟槽隔离层凹陷，在所得结构上形成覆盖键图案。 通过使用原位处理从所得结构中除去光致抗蚀剂图案。 然后，对所得结构进行原位清洗处理。

公开(公告)号：KR1020070002630A

公开(公告)日：2007-01-05

申请号：KR1020050058242

申请日：2005-06-30

申请人： 에스케이하이닉스 주식회사

发明人： 최중일

IPC分类号： H01L21/027

CPC分类号： G03F1/42 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54426

摘要： An exposure mask of a semiconductor device and a semiconductor device forming method are provided to improve stability and reliability of a semiconductor device manufacturing process by checking easily the result of an exposure process using an improved inner bar structure composed of two or more bars parallel with each other. An exposure mask of a semiconductor device includes a quartz substrate, an outer bar(11) used as a first light shielding pattern on the quartz substrate, and an inner bar(13) used as a second light shielding pattern. The inner bar is composed of at least two or more bar type structures parallel with each other.

摘要翻译： 提供了半导体器件的曝光掩模和半导体器件形成方法，以通过使用由两个或更多个与每个的平行的两个或更多个棒组成的改进的内部棒结构来容易地检查曝光处理的结果来提高半导体器件制造工艺的稳定性和可靠性 其他。 半导体器件的曝光掩模包括石英衬底，用作石英衬底上的第一遮光图案的外杆（11）和用作第二遮光图案的内杆（13）。 内杆由至少两个或更多个彼此平行的条形结构构成。

公开(公告)号：KR1020060135122A

公开(公告)日：2006-12-29

申请号：KR1020050054799

申请日：2005-06-24

申请人： 삼성전자주식회사

发明人： 김대중 ,  이대엽 ,  유지용 ,  서전석 ,  유도열

IPC分类号： H01L21/027

CPC分类号： H01L23/544 ,  G03F7/70633 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  G03F9/708 ,  H01L2223/54426 ,  H01L2924/00

摘要： An overlay key, a method of forming the same, a semiconductor device fabricated by using the same, and a method of fabricating a semiconductor device by using the same are provided to obtain a clear overlay key image by using the overlay key in which a film having high reflectivity is formed under a main scale. An overlay key includes a main scale(224) formed on a metal silicide film directly contacting a silicon substrate, and a vernier(254) provided on the main scale. The metal silicide is obtained by reacting the substrate(200) with a metal material. The metal silicide contains cobalt silicide, tungsten silicide, titanium silicide, and tantalum silicide. The metal silicide has reflectivity of 8 to 30%.

摘要翻译： 提供一种覆盖键，其形成方法，使用该半导体器件的半导体器件，以及通过使用该半导体器件制造半导体器件的方法，通过使用覆盖键来获得清晰的覆盖键图像， 在主刻度上形成具有高反射率的。 覆盖键包括形成在与硅衬底直接接触的金属硅化物膜上的主刻度（224）和设置在主刻度上的游标（254）。 金属硅化物通过使基板（200）与金属材料反应而获得。 金属硅化物包含硅化钴，硅化钨，硅化钛和硅化钽。 金属硅化物的反射率为8〜30％。