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    반도체 장치
    4.
    发明公开
    반도체 장치 审中-实审
    半导体器件

    公开(公告)号：KR1020120122912A

    公开(公告)日：2012-11-07

    申请号：KR1020120042590

    申请日：2012-04-24

    Applicant: 가부시키가이샤 한도오따이 에네루기 켄큐쇼

    Inventor： 이에다요시노리 ,  이소베아츠오 ,  시오노이리유타카 ,  아츠미토모아키

    IPC: H01L27/06 ,  H01L27/11 ,  G11C7/00

    Abstract: PURPOSE: A semiconductor device is provided to secure high speed operation and reduce power consumption. CONSTITUTION: A semiconductor film(103n) has silicon having crystallization. A gate insulating film(104n) is formed on the semiconductor film. A gate electrode(105n) is arranged on the area overlapped with the semiconductor film. A conductive film(161,162) is connected to the semiconductor film and operated as a source electrode or a drain electrode. The semiconductor film includes a first area(108) serving as a channel formation area and second areas(109,110) serving as a source and a drain. A p-channel transistor(102p) includes a semiconductor film(103p), a gate insulating film(104p) and a gate electrode(105p).

    Abstract translation: 目的：提供半导体器件以确保高速运行并降低功耗。 构成：半导体膜（103n）具有结晶化的硅。 在半导体膜上形成栅绝缘膜（104n）。 栅电极（105n）配置在与半导体膜重叠的区域上。 导电膜（161,162）连接到半导体膜并用作源电极或漏电极。 半导体膜包括用作沟道形成区域的第一区域（108）和用作源极和漏极的第二区域（109,110）。 p沟道晶体管（102p）包括半导体膜（103p），栅极绝缘膜（104p）和栅电极（105p）。

    반도체 장치 및 상기 반도체 장치의 제작 방법
    5.
    发明公开
    반도체 장치 및 상기 반도체 장치의 제작 방법 审中-实审
    半导体器件及其制造方法

    公开(公告)号：KR1020120120062A

    公开(公告)日：2012-11-01

    申请号：KR1020120041410

    申请日：2012-04-20

    Applicant: 가부시키가이샤 한도오따이 에네루기 켄큐쇼

    Inventor： 이소베아츠오 ,  사사끼도시나리 ,  사사가와신야 ,  이시즈까아끼히로

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/78603

    Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to extend an effective channel length and implement a fine transistor by forming a channel region of an oxide semiconductor layer in contact with a convex structure of an insulation layer. CONSTITUTION: An insulation layer(130) with a convex part(131) is formed on a substrate. An oxide semiconductor layer(144) is formed on the insulation layer. A gate insulation layer(146) is formed on the oxide semiconductor layer. A gate electrode(148) is formed on the gate insulation layer. A source electrode(142a) and a drain electrode(142b) are electrically connected to the oxide semiconductor layer.

    Abstract translation: 目的：提供半导体器件及其制造方法，以通过形成与绝缘层的凸形结构接触的氧化物半导体层的沟道区域来延长有效沟道长度并实现精细晶体管。 构成：在基板上形成具有凸部（131）的绝缘层（130）。 在绝缘层上形成氧化物半导体层（144）。 在氧化物半导体层上形成栅极绝缘层（146）。 栅电极（148）形成在栅绝缘层上。 源电极（142a）和漏电极（142b）电连接到氧化物半导体层。

    반도체 장치의 제작 방법
    6.
    发明公开
    반도체 장치의 제작 방법 审中-实审
    半导体器件的制造方法

    公开(公告)号：KR1020120114169A

    公开(公告)日：2012-10-16

    申请号：KR1020120034833

    申请日：2012-04-04

    Applicant: 가부시키가이샤 한도오따이 에네루기 켄큐쇼

    Inventor： 사토유헤이 ,  사토케이지 ,  사사키도시나리 ,  마루야마테츠노리 ,  이소베아츠오 ,  무라카와츠토무 ,  테즈카사치아키

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/7869 ,  H01L21/477 ,  H01L29/66742 ,  H01L21/324 ,  H01L29/78606

    Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to prevent water or hydrogen to be entered in an oxide semiconductor layer by forming an oxide aluminum film on an insulating layer and a gate electrode layer. CONSTITUTION: A gate insulating layer(110) is formed on an oxide semiconductor layer(106). A gate electrode layer(112) is formed on the oxide semiconductor layer. The gate insulating layer is placed between the oxide semiconductor layer and the gate electrode layer. An oxide aluminum film is formed on the gate electrode layer. A thermal process is processed to the oxide semiconductor layer. The thickness of the oxide aluminum film is 50nm to 500nm. An inter-layer insulating film is formed on the oxide aluminum film.

    Abstract translation: 目的：提供一种制造半导体器件的方法，以通过在绝缘层和栅电极层上形成氧化铝膜来防止水或氢进入氧化物半导体层。 构成：在氧化物半导体层（106）上形成栅极绝缘层（110）。 在氧化物半导体层上形成栅电极层（112）。 栅极绝缘层位于氧化物半导体层和栅电极层之间。 在栅电极层上形成氧化铝膜。 对氧化物半导体层进行热处理。 氧化铝膜的厚度为50nm至500nm。 在氧化铝膜上形成层间绝缘膜。

    반도체 장치의 제작 방법
    10.
    发明公开
    반도체 장치의 제작 방법 审中-实审
    制造半导体器件的方法

    公开(公告)号：KR1020140053932A

    公开(公告)日：2014-05-08

    申请号：KR1020140044318

    申请日：2014-04-14

    Applicant: 가부시키가이샤 한도오따이 에네루기 켄큐쇼

    Inventor： 사이토도시히코 ,  이소베아츠오 ,  하나오카가즈야 ,  고에즈카준이치 ,  사사가와신야 ,  구라타모토무 ,  이시즈카아키히로

    IPC: H01L29/786 ,  H01L21/336 ,  H01L21/31

    CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78603

    Abstract: Provided is a transistor of a micro structure with good throughput. Also, provided is a semiconductor device which has high response and high operation by improving the on property of the transistor. An oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conducive layer, an interlayer dielectric are successively stacked. The gate electrode layer and the conductive layer on the insulating layer are removed by cutting the conductive layer. An electrode layer which has a source electrode layer and a drain electrode layer and touches the oxide semiconductor layer is formed by being overlapped with a region which touches the source electrode layer and the drain electrode layer.

    Abstract translation: 提供了具有良好生产能力的微结构的晶体管。 此外，提供了通过提高晶体管的导通性而具有高响应性和高操作性的半导体器件。 依次层叠氧化物半导体层，栅极绝缘层，栅电极层，绝缘层，导电层，层间电介质。 通过切割导电层来去除绝缘层上的栅电极层和导电层。 通过与接触源极电极层和漏极电极层的区域重叠，形成具有源极电极层和漏极电极层并与氧化物半导体层接触的电极层。

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