公开(公告)号：US4964142A

公开(公告)日：1990-10-16

申请号：US72955

申请日：1987-07-15

Applicant: Kadiresan Annamalai

Inventor： Kadiresan Annamalai

IPC: H04L7/00 ,  H04J3/06

CPC classification number: H04J3/0632

Abstract: Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

公开(公告)号：US4617478A

公开(公告)日：1986-10-14

申请号：US530176

申请日：1983-09-07

Applicant: Hemmige D. Varadarajan

Inventor： Hemmige D. Varadarajan

IPC: H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086 ,  H03K19/082 ,  H03K19/092

CPC classification number: H03K19/086 ,  H03K19/013

Abstract: In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.

Abstract translation: 根据本发明，在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关的参考部分通过引入一个慢速装置作为参考元件来修改，以增强输入元件的导通和关断速度 。 特别地，传统的ECL逆变器栅极或常规CML反相器栅极的参考晶体管被替换为慢晶体管或慢二极管，以便绕过发射极动态电阻。 因此，参考元件QR的发射极时间常数增加，使得当输入元件的基极瞬时变化时，公共电流源节点（节点3）上的电压基本上不变化。 因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。

公开(公告)号：US20250107045A1

公开(公告)日：2025-03-27

申请号：US18471888

申请日：2023-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Girish Anant Kini ,  Shardul Suresh Adkar ,  Salvador D. Jimenez, III ,  Mark Steinke ,  Ethan Cruz ,  Edgar Stone ,  Ahmed Mohamed Abou-Alfotouh

IPC: H05K7/20

Abstract: A method for cooling accelerators having back side power delivery components can include providing a printed circuit board having a first side that includes an integrated circuit and a first set of one or more power delivery components and a second side that is opposite the first side and that includes a second set of one or more power delivery components. The method can also include positioning a first cooling system to cool the integrated circuit and the first set of one or more power delivery components. The method can further include positioning a second cooling system to cool the second set of one or more power delivery components. Various other methods and systems are also disclosed.

公开(公告)号：US20250106155A1

公开(公告)日：2025-03-27

申请号：US18373908

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajshekhar BIRADAR ,  Sunil KULKARNI ,  Manjunath SHIVANNA

IPC: H04L45/745 ,  H04L9/40 ,  H04L45/00

Abstract: Embodiments herein describe tokenizing a data sequence to perform a wildcard lookup. For example, a network device (such as a NIC or a switch) can receive a data sequence (e.g., an IP address, Uniform Resource Locator (URL), domain name, etc.) which can be broken down into separate tokens. After identifying a first token, the network device can search a wildcard lookup table to determine a first entry in the table that matches the first token. Assuming there is a match, the network device can identify an action associated with the entry. If the action is to continue with the search, the network device can then retrieve a key from the entry which it then combines with a second token in the data sequence to again search the wildcard lookup table.

公开(公告)号：US20250103424A1

公开(公告)日：2025-03-27

申请号：US18653719

申请日：2024-05-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David Da-Wei LIN ,  Edoardo PRETE ,  Tsun-Ho LIU

IPC: G06F11/10

Abstract: A memory system includes a memory controller and memory circuitry. The memory controller outputs a first training signal. The memory circuitry is coupled to the memory controller. The memory circuitry includes a memory device and multiplexing data buffer circuitry. The multiplexing data buffer circuitry is coupled to the memory device. The multiplexing data buffer circuitry includes first circuitry and second circuitry. The second circuitry is coupled to the memory device. The second circuitry receives the first training signal from memory controller comprising first training data associated with the first circuitry, writes the first training data to the memory device, and read the written first training data from the memory device, and outputs the written first training data to the memory controller. The memory controller is configured to determine equalization parameters for the first circuitry based on the written first training data.

公开(公告)号：US20250103395A1

公开(公告)日：2025-03-27

申请号：US18476071

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford Beckmann ,  Matthew David Sinclair ,  Vinay Bharadwaj Ramakrishnaiah ,  William Peter Ehrett

IPC: G06F9/50

Abstract: A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method can further include completing, by the at least one processor and in response to a determination that the one or more shared resources is available, execution of the one or more processes. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250103371A1

公开(公告)日：2025-03-27

申请号：US18472924

申请日：2023-09-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： JinYun Liu ,  Yinan Jiang ,  HaiJun Chang

IPC: G06F9/455

Abstract: The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250103360A1

公开(公告)日：2025-03-27

申请号：US18472007

申请日：2023-09-21

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Ananta S. Pallapothu ,  Raghukul Bhushan Dikshit

IPC: G06F9/455

Abstract: A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to synchronize the request data from an originator clock domain to a transceiver clock domain operating at a higher frequency than the originator clock domain. The first IC includes a first transceiver circuit configured to convey the request data over a communication link that operates asynchronously to the originator clock domain.

公开(公告)号：US20250103342A1

公开(公告)日：2025-03-27

申请号：US18475918

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Ryan Lynn Swann ,  Alexander Sean Underwood ,  Derrick A. Aguren ,  Karthik Ramu Sangaiah ,  Sumanth Gudaparthi ,  Rose R. Thompson

IPC: G06F9/38

Abstract: A method, apparatus and computer readable medium that use of a lightweight finite state machine (FSM) control flow block to enable limited execution of data-dependent control flow, thereby enhancing the control flow flexibility of array scale SIMD processors. In certain cases, the FSM block contains registers responsible for decoding and managing single global instructions into multiple local instructions that can incorporate data-dependent control flow.

公开(公告)号：US20250103340A1

公开(公告)日：2025-03-27

申请号：US18475507

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Upamanyu Banerjee ,  Arun A. Nair

IPC: G06F9/30

Abstract: A computer-implemented method for resynchronization at execution time can include detecting, by at least one processor and during an execution time of an instruction, a resynchronization. The method can additionally include regenerating, by the at least one processor and in response to the detection, an instruction pointer. The method can also include performing, by the at least one processor and during the execution time of the instruction, the resynchronization by using the regenerated instruction pointer. Various other methods and systems are also disclosed.