公开(公告)号：US20200144097A1

公开(公告)日：2020-05-07

申请号：US16180691

申请日：2018-11-05

Applicant: Lam Research Corporation

Inventor： Peter S. Thaulad ,  Brett M. Herzig ,  Richard M. Blank ,  Benjamin W. Mooring

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/68

Abstract: Systems and techniques for determining and correcting inter-wafer misalignments in a stack of wafers transported by a wafer handling robot are discussed. An enhanced automatic wafer centering system is provided that may be used to determine a smallest circle associated with the stack of wafers, which may then be used to determine whether or not the stack of wafer meets various process requirements and/or if a centering correction can be made to better align the wafers with a receiving station coordinate frame.

公开(公告)号：US20250062106A1

公开(公告)日：2025-02-20

申请号：US18719822

申请日：2022-12-12

Applicant: Lam Research Corporation

Inventor： Danae Nicole Kay ,  Thomas Mark Pratt ,  Matthew Palmer Kwan

IPC: H01J37/32 ,  C23C16/44

Abstract: A gas delivery apparatus includes an inlet portion and an outlet portion. The inlet portion can comprise a plurality of inlet ports configured to receive gas from a gas source. The inlet portion can also comprise a corresponding plurality of tapered surfaces associated with the plurality of inlet ports. Each tapered surface of the plurality of tapered surfaces surrounds a corresponding inlet port of the plurality of inlet ports. The outlet portion can be configured to deliver the gas to a gas showerhead of a process chamber. Each tapered surface of the plurality of tapered surfaces can comprise a first region and a second region. The first region is associated with a first curvature. The second region is associated with a second curvature. The first curvature can be different from the second curvature.

公开(公告)号：US20250060673A1

公开(公告)日：2025-02-20

申请号：US18719815

申请日：2022-12-16

Applicant: Lam Research Corporation

Inventor： Chenghao Wu ,  Eric Calvin Hansen ,  Timothy William Weidman ,  Jason Philip Coyle ,  Raymond Nicholas Vrtis

IPC: G03F7/36 ,  G03F7/00 ,  G03F7/32 ,  G03F7/40 ,  H01L21/027

Abstract: The present disclosure relates to use of an acid for developing or treating a radiation-sensitive film including two or more elements having a high patterning radiation-absorption cross-section. The acid can be employed to form a pattern by a negative tone development process or to treat a developed pattern by further removing residual resist components.

公开(公告)号：US12230482B2

公开(公告)日：2025-02-18

申请号：US16497091

申请日：2017-07-24

Applicant: LAM RESEARCH CORPORATION

Inventor： Hiran Rajitha Rathnasinghe ,  Jon Mcchesney

IPC: H01J37/32 ,  H01L21/683 ,  H01L21/687

Abstract: An edge ring is configured to be raised and lowered relative to a substrate support, via one or more lift pins, in a substrate processing system. The edge ring is further configured to interface with a guide feature extending upward from a bottom ring and/or a middle ring of the substrate support during tuning of the edge ring. The edge ring includes an upper surface, an annular inner diameter, an annular outer diameter, a lower surface, and an annular groove arranged in the lower surface of the edge ring to interface with the guide feature. Walls of the annular groove are substantially vertical.

公开(公告)号：US20250054788A1

公开(公告)日：2025-02-13

申请号：US18929547

申请日：2024-10-28

Applicant: Lam Research Corporation

Inventor： Changyou Jing

IPC: H01L21/67 ,  H03K3/017 ,  H03K5/156 ,  H05B1/02

Abstract: Systems and methods for identifying a single failure in a heater array and compensating for the failure are described. The methods include identifying two X buses and two Y buses of the heater array having a location of the failure. A confirmation of the single failure within the heater array is performed after identifying the two X and two Y buses. Once the single failure is confirmed, the location of the failure is identified. The methods include compensating for the single failure by adjusting a duty cycle of a heater at the location of the failure, adjusting additional duty cycles of heaters along the same X bus as the failed heater and the same Y bus as the failed heater, and maintaining remaining duty cycles of power provided to remaining heaters of the heater array.

公开(公告)号：US20250054778A1

公开(公告)日：2025-02-13

申请号：US18719047

申请日：2022-12-08

Applicant: LAM RESEARCH CORPORATION

Inventor： Anthony DE LA LLERA ,  Pratik MANKIDY ,  John HOLLAND

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/687

Abstract: An assembly for a processing chamber of a substrate processing system includes a first component, a second component, and a thermal interface material arranged between the first component and the second component. At least one of the first component and the second component is configured to be exposed to plasma within the processing chamber, the thermal interface material has a first surface that faces and is in direct contact with the first component and a second surface that faces and is in direct contact with the second component the thermal interface material is comprised of a silicon polymer with at least one of aligned carbon fibers and carbon nanotubes (CNTs), wherein the at least one of the carbon fibers and the CNTs are aligned in a direction perpendicular to the first surface and the second surface.

公开(公告)号：US20250054769A1

公开(公告)日：2025-02-13

申请号：US18724531

申请日：2022-12-05

Applicant: Lam Research Corporation

Inventor： Hsu-Cheng HUANG ,  Sang Jun CHO ,  Sriharsha JAYANTI ,  Gerardo DELGADINO ,  Steven CHUANG

IPC: H01L21/3105 ,  H01L21/311

Abstract: A patterning method includes etching a mask formed above a stack of two or more layers where the mask comprises a first patterned structure, a second patterned structure above the first patterned structure, where portions of the second patterned structure intersect the first patterned structure to form intersections and at least an opening. The mask includes a structure vertically between portions of the second patterned structure and the stack. The method includes etching a first layer of the stack through the opening and exposing a top surface of a second layer below the first layer, etching and removing the first patterned structure and the second patterned structure selectively to the first layer and the top surface of the second layer to form a planar mask comprising the first layer. The method further includes etching the second layer of the stack using the planar mask.

公开(公告)号：US20250054747A1

公开(公告)日：2025-02-13

申请号：US18717975

申请日：2022-12-01

Applicant: Lam Research Corporation

Inventor： Awnish Gupta ,  Bart J. Van Schravendijk ,  Dustin Zachary Austin ,  Frank Loren Pasquale

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/027 ,  H01L21/768

Abstract: High quality silicon nitride (silicon nitride characterized by low wet etch rate in dilute hydrofluoric acid) is deposited on a semiconductor substrate having one or more recessed features in a highly conformal manner. The deposition involves exposing the semiconductor substrate to a silicon-containing precursor (e.g., an aminosilane) to form an adsorbed layer of the silicon-containing precursor on the substrate. The adsorbed layer is then treated with a plasma formed in a process gas that includes N2, at a temperature of 300-750° C. and a pressure of at least about 15 Torr (e.g., 15-30 Torr) to convert the precursor to silicon nitride. The exposure to precursor and conversion to silicon nitride are repeated in the same process chamber over many deposition cycles until a conformal silicon nitride of desired thickness is formed. In some embodiments the deposited films are hydrogen-free as evidenced by IR spectra.

公开(公告)号：US20250046572A1

公开(公告)日：2025-02-06

申请号：US18693940

申请日：2022-09-22

Applicant: Lam Research Corporation

Inventor： Juline Shoeb ,  Myeong Yeol Choi ,  Alexander Miller Paterson ,  Yuhou Wang

IPC: H01J37/32

Abstract: A method for operating a plasma chamber to increase ion energy and decrease angular spread of ions during an etch operation is described. Method includes placing a substrate on an electrostatic chuck within the plasma chamber, wherein the electrostatic chuck is electrically coupled to a node. Method further includes forming a plasma in the plasma chamber, where the plasma produces a sheath with a first sheath voltage. The method further includes increasing the first sheath voltage to a second sheath voltage by applying a non-sinusoidal voltage at the electrostatic chuck and by applying a sinusoidal voltage at the electrostatic chuck, where a sum of the non-sinusoidal voltage and the sinusoidal voltage creates a voltage response on the electrostatic chuck that effectuates a change in a spread in ion energy at the wafer.

公开(公告)号：US20250043421A1

公开(公告)日：2025-02-06

申请号：US18715203

申请日：2022-12-07

Applicant: LAM RESEARCH CORPORATION

Inventor： Michael Philip ROBERTS ,  Bharath Kumar SEETHARAMA ,  Ryan BLAQUIERE

IPC: C23C16/455 ,  C23C16/52

Abstract: A substrate processing system includes N valve systems connected to N stations, respectively. Each valve system includes a manifold block, a plurality of valves, and a flow control device. The manifold block includes inlets to receive a process gas and an inert gas, an outlet connected to a station, and a plurality of gas flow channels disposed within the manifold block and connected to the inlets and the outlet. The valves are mounted to the manifold block and control flow of the process gas and the inert gas through the outlet. The flow control device is mounted to the manifold block and controls flow of the inert gas through the manifold block into the one of the N stations. The flow control device of each of the N valve systems is calibrated to balance the flow of the inert gas in the N stations.