公开(公告)号：US08193537B2

公开(公告)日：2012-06-05

申请号：US11764606

申请日：2007-06-18

申请人： Michael S. Mazzola

发明人： Michael S. Mazzola

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L31/028 ,  H01L31/0312 ,  H01L31/09 ,  H01L31/1105 ,  H03K17/78 ,  Y10S438/917 ,  Y10S438/931

摘要： An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.

摘要翻译： 与用于影响电力电子设备和电路的光学控制的常规方法相比，使用光学活性材料来产生具有显着性能优点的功率器件和电路。 通过用硼相关的D中心补偿浅供体来形成碳化硅光学活性材料。 所得到的材料可以是n型或p型，但是当通过电磁辐射照射时能够引起持续光电导的能力与其它材料不同，其中光子能量超过光电从D激发电子所需的阈值能量 - 允许状态接近导带边缘，其从多形型到多型变化。

公开(公告)号：US08183124B2

公开(公告)日：2012-05-22

申请号：US12881771

申请日：2010-09-14

申请人： Michael S. Mazzola

发明人： Michael S. Mazzola

IPC分类号： H01L21/76

CPC分类号： H01L21/8213 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

摘要翻译： 制造半绝缘外延层的方法包括用硼离子注入在衬底上形成的衬底或第一外延层，以在衬底的表面上或第一外延层的表面上形成硼注入区，并且生长 在所述衬底的硼注入区或所述第一外延层的硼注入区上的第二外延层，以形成半绝缘外延层。

公开(公告)号：US20130009169A1

公开(公告)日：2013-01-10

申请号：US13613295

申请日：2012-09-13

申请人： Lin Cheng

发明人： Lin Cheng

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/732 ,  H01L21/336

CPC分类号： H01L29/8083 ,  H01L29/1004 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/6631 ,  H01L29/66924 ,  H01L29/732

摘要： Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.

摘要翻译： 描述了制造诸如垂直结型场效应晶体管（VJFET）或双极结型晶体管（BJT）的半导体器件的方法。 该方法不需要离子注入。 VJFET器件具有外延再生长的n型沟道层和外延再生长的p型栅极层以及外延生长的掩埋栅极层。 还描述了通过该方法制造的装置。

公开(公告)号：US08338255B2

公开(公告)日：2012-12-25

申请号：US12818281

申请日：2010-06-18

申请人： Lin Cheng

发明人： Lin Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/8083 ,  H01L29/1004 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/6631 ,  H01L29/66924 ,  H01L29/732

摘要： Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.

摘要翻译： 描述了制造诸如垂直结型场效应晶体管（VJFET）或双极结型晶体管（BJT）的半导体器件的方法。 该方法不需要离子注入。 VJFET器件具有外延再生长的n型沟道层和外延再生长的p型栅极层以及外延生长的掩埋栅极层。 还描述了通过该方法制造的装置。

公开(公告)号：US20120309154A1

公开(公告)日：2012-12-06

申请号：US13587151

申请日：2012-08-16

申请人： Igor SANKIN ,  Joseph Neil MERRETT

发明人： Igor SANKIN ,  Joseph Neil MERRETT

IPC分类号： H01L21/336

CPC分类号： H01L29/868 ,  H01L29/1608 ,  H01L29/872

摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

摘要翻译： 描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。 该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。 该器件可以制成诸如SiC的宽带隙半导体材料。 该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。

公开(公告)号：US20120305994A1

公开(公告)日：2012-12-06

申请号：US13585183

申请日：2012-08-14

申请人： Joseph Neil MERRETT ,  Igor SANKIN

发明人： Joseph Neil MERRETT ,  Igor SANKIN

IPC分类号： H01L29/808 ,  H01L29/732

CPC分类号： H01L29/66068 ,  H01L29/732 ,  H01L29/808

摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

摘要翻译： 描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。 所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。 还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。 半导体器件可以制成碳化硅。

公开(公告)号：US08269262B2

公开(公告)日：2012-09-18

申请号：US11836994

申请日：2007-08-10

申请人： Igor Sankin ,  Joseph Neil Merrett

发明人： Igor Sankin ,  Joseph Neil Merrett

IPC分类号： H01L29/66

CPC分类号： H01L29/868 ,  H01L29/1608 ,  H01L29/872

摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

摘要翻译： 描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。 该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。 该器件可以制成诸如SiC的宽带隙半导体材料。 该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。

公开(公告)号：US20120199940A1

公开(公告)日：2012-08-09

申请号：US13449502

申请日：2012-04-18

申请人： Michael S. MAZZOLA

发明人： Michael S. MAZZOLA

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/8213 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

摘要翻译： 制造半绝缘外延层的方法包括用硼离子注入在衬底上形成的衬底或第一外延层，以在衬底的表面上或第一外延层的表面上形成硼注入区，并且生长 在所述衬底的硼注入区或所述第一外延层的硼注入区上的第二外延层，以形成半绝缘外延层。

公开(公告)号：US20130011979A1

公开(公告)日：2013-01-10

申请号：US13613453

申请日：2012-09-13

申请人： Andrew RITENOUR ,  David C. SHERIDAN

发明人： Andrew RITENOUR ,  David C. SHERIDAN

IPC分类号： H01L21/337

CPC分类号： H01L29/8083 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/7722

摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

摘要翻译： 描述了具有自对准引脚，p + / n / n +或p + / p / n +栅 - 源极结的垂直结型场效应晶体管（VJFET）。 为了保持良好的高电压性能（即低DIBL），器件栅极可以自对准至0.5μm以内，同时减少反向偏压下的栅 - 源结泄漏。 该器件可以是宽带隙半导体器件，例如SiC垂直沟道结场效应。 还描述了制造该装置的方法。

公开(公告)号：US08169022B2

公开(公告)日：2012-05-01

申请号：US12818232

申请日：2010-06-18

申请人： Lin Cheng ,  Michael Mazzola

发明人： Lin Cheng ,  Michael Mazzola

IPC分类号： H01L29/66

CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/868 ,  H01L29/872

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）或二极管，例如结型势垒肖特基（JBS）二极管或PiN二极管。 器件具有通过外延生长形成的渐变p型半导体层和/或区域。 该方法不需要离子注入。 这些器件可以由诸如碳化硅（SiC）的宽带隙半导体材料制成，并且可以用于高温和高功率应用中。