公开(公告)号：US20250106508A1

公开(公告)日：2025-03-27

申请号：US18476011

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Po-Min Wang

IPC: H04N23/68 ,  H04N5/265

Abstract: A technique for generating video is provided. The technique includes obtaining a plurality of source frames with a wide-angle camera and a narrow-angle camera; identifying a plurality of central portions and a plurality of peripheral portions of the plurality of source frames based on image stabilization; and combining the plurality of central portions and the plurality of peripheral portions to generate a plurality of resulting frames of an output video.

公开(公告)号：US20250103650A1

公开(公告)日：2025-03-27

申请号：US18371010

申请日：2023-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Jagadish B. Kotra

IPC: G06F16/901

Abstract: Graph analytics system are described. In accordance with the described techniques, a graph having vertices that include a first vertex and a second vertex that are associated with access control metadata are received. An updated graph is output based on a merging of the first vertex and the second vertex into a merged vertex of a group of vertices based on the first vertex and the second vertex being associated with access control metadata common to the first vertex and the second vertex and based on a reordering technique. A single copy of the access control metadata is stored for the first vertex and the second vertex.

公开(公告)号：US20250103297A1

公开(公告)日：2025-03-27

申请号：US18372593

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Changhoon YEO ,  Tun-Fen WANG ,  Ajay K. DAWRA

IPC: G06F7/58

Abstract: Techniques for detecting a digital pseudo-random sequence (PRS) using fast locking, including repeatedly computing a first PRS seed based on an ADC output, generating a PRS sequence based on the first seed, computing a second PRS seed based on the sequence, and comparing the sequence to the ADC output (comparison results may be provided as a bool signal), until the sequence matches the ADC output. Thereafter, the technique may include re-computing the sequence based on the second seed, re-computing the second seed based on the re-computed sequence and comparing the re-computed sequence to the ADC output. The technique may further include setting a lock when a threshold number of sequences computed from the second seed match the ADC output, and reverting to computing the sequence based on the first seed if a sequence computed from the second seed does not match the ADC output and the lock is not set.

公开(公告)号：US20250098184A1

公开(公告)日：2025-03-20

申请号：US18470582

申请日：2023-09-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Arsalan Alam ,  Anadi Srivastava ,  Rajen Singh Sidhu ,  Alexander Helmut Pfeiffenberger ,  Liwei Wang

IPC: H01L23/522 ,  H01L23/64

Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more tiers of trench capacitors.

公开(公告)号：US20250096136A1

公开(公告)日：2025-03-20

申请号：US18471114

申请日：2023-09-20

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Divya Madapusi Srinivas Prasad ,  Gabriel H. Loh ,  Richard Schultz ,  Jeffrey Richard Rearick ,  Shidhartha Das ,  Suresh Ramalingam

IPC: H01L23/528 ,  H01L23/48

Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.

公开(公告)号：US12254353B2

公开(公告)日：2025-03-18

申请号：US17564092

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Zhuo Chen ,  Steven J. Tovey

IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

Abstract: In order to efficiently process graphics data, operations are performed including allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.

公开(公告)号：US12254196B2

公开(公告)日：2025-03-18

申请号：US18057539

申请日：2022-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Raul Gutierrez

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and prefetch one or more additional data items from memory. The first data and prefetched data are stored in a locally accessible buffer of the I/O controller. The I/O controller is then configured to convey each of the first data and one or more data items from the buffer to the I/O device at regular intervals of time during a given period of time, prior to initiating a fetch of additional data from the memory. During the given period of time, the power management circuitry is configured to cause at least the memory to enter a reduced power state.

公开(公告)号：US12253892B2

公开(公告)日：2025-03-18

申请号：US17704912

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Amitabh Mehra ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/20 ,  H05K5/02 ,  H05K5/03 ,  H05K7/20

Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.

公开(公告)号：US12248789B2

公开(公告)日：2025-03-11

申请号：US18309536

申请日：2023-04-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. Kazakov

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.

公开(公告)号：US20250080471A1

公开(公告)日：2025-03-06

申请号：US18620838

申请日：2024-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajshekhar BIRADAR

IPC: H04L47/36

Abstract: Embodiments herein describe creating multiple packet fragments from a large packet that, for example, exceeds a maximum transmission unit (MTU) supported by a network. In one embodiment, a network interface card or controller (NIC) replicates the large packet to form multiple copies (i.e., replicated packets). The number of replications can correspond to the number of fragments needed so the MTU is not exceeded. In one embodiment, the NIC assigns an identifier, such as an ID or a count value, to each replicated packet. The NIC can use the identifier to selectively remove portions of the payloads of the replicated packets (i.e., shrink the packets) so that the combined payloads (or union) of the packet fragments is the same as the payload in the large packet.