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公开(公告)号：US20240403121A1
公开(公告)日：2024-12-05
申请号：US18203360
申请日：2023-05-30
Applicant: Advanced Micro Devices, Inc , ATI Technologies ULC
Inventor： Anil Harwani , Paul Blinzer , Kenneth Lawrence Mitchell , Adam Neil Calder Clark , Amitabh Mehra , Joshua Taylor Knight , Grant Evan Ley , Jerry Anton Ahrens , William Robert Alverson
IPC: G06F9/50
Abstract: Task scheduling based on component margins is described. In accordance with the described techniques, a scheduler of an operating system accesses a margin table when a request to perform tasks is received. The scheduler schedules tasks on various components of a system based on margins of those components. When a request to perform a task is received, for example, the scheduler accesses the margin table and selects a component to perform the task based on the margin information included in the margin table as well as based on the task, such as whether the task benefits more from being performed fast or being performed accurately. The scheduler then schedules the task using the selected component.
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公开(公告)号：US20240143445A1
公开(公告)日：2024-05-02
申请号：US17974981
申请日：2022-10-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Alicia Wen Ju Yurie Leong , William Robert Alverson , Joshua Taylor Knight , Jerry Anton Ahrens , Grant Evan Ley , Anil Harwani , Amitabh Mehra , Jayesh Hari Joshi
CPC classification number: G06F11/1417 , G11C29/52
Abstract: Stability testing for memory overclocking is described. In accordance with the described techniques, operation of a memory with overclocked memory settings is testing during a boot up process of a computing device. Test results based on the testing are exposed via a user interface. The test results predict a stability of the memory over a subsequent time period if the memory is configured to operate with the overclocked memory settings.
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公开(公告)号：US20240053891A1
公开(公告)日：2024-02-15
申请号：US17887245
申请日：2022-08-12
Applicant: Advanced Micro Devices, Inc.
Inventor： William Robert Alverson , Amitabh Mehra , Jerry Anton Ahrens , Grant Evan Ley , Anil Harwani , Joshua Taylor Knight
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0673 , G06F3/0655
Abstract: Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.
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公开(公告)号：US20230315171A1
公开(公告)日：2023-10-05
申请号：US17704912
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Jerry Anton Ahrens , William Robert Alverson , Amitabh Mehra , Grant Evan Ley , Anil Harwani , Joshua Taylor Knight
CPC classification number: G06F1/206 , H05K5/0213 , H05K5/0239 , H05K7/20209
Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.
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公开(公告)号：US20240220208A1
公开(公告)日：2024-07-04
申请号：US18147257
申请日：2022-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Jerry Anton Ahrens , William Robert Alverson , Amitabh Mehra , Grant Evan Ley , Joshua Taylor Knight , Anil Harwani , Jayesh Hari Joshi
IPC: G06F7/58
CPC classification number: G06F7/588
Abstract: Induced signal marginality for random number generation is described. In accordance with the described techniques, a pseudorandom number is transmitted across an interface while the interface is operated with settings configured to cause instability in the interface. A random number is received as an output of the interface. The settings configured to cause instability in the interface include overclocked settings of interface operating parameters.
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Patent Agency Ranking
公开(公告)号：US20240211416A1
公开(公告)日：2024-06-27
申请号：US18146920
申请日：2022-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Jerry Anton Ahrens , William Robert Alverson , Joshua Taylor Knight , Amitabh Mehra , Anil Harwani , Grant Evan Ley
IPC: G06F13/16
CPC classification number: G06F13/1668 , G06F13/1626 , G06F13/1642
Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.
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公开(公告)号：US20230350696A1
公开(公告)日：2023-11-02
申请号：US17732741
申请日：2022-04-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Anil Harwani , William Robert Alverson , Amitabh Mehra , Jerry Anton Ahrens , Grant Evan Ley , Joshua Taylor Knight
IPC: G06F9/445
CPC classification number: G06F9/44505
Abstract: Real time workload-based system adjustment is described. In accordance with the described techniques, a processor and a memory are operated according to first settings associated with a first workload. A second workload configured to utilize the processor and the memory is detected. The second workload is associated with second settings. Responsive to detecting the second workload, operation of the processor and the memory are adjusted to operate according to the second settings without rebooting.
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公开(公告)号：US20230315191A1
公开(公告)日：2023-10-05
申请号：US17708453
申请日：2022-03-30
Applicant: Advanced Micro Devices, Inc.
Inventor： William Robert Alverson , Amitabh Mehra , Jerry Anton Ahrens , Grant Evan Ley , Anil Harwani , Joshua Taylor Knight
IPC: G06F1/3287 , G06F9/445 , G06F1/3206
CPC classification number: G06F1/3287 , G06F9/44505 , G06F1/3206
Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.
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公开(公告)号：US20240319903A1
公开(公告)日：2024-09-26
申请号：US18187900
申请日：2023-03-22
Applicant: Advanced Micro Devices, Inc.
Inventor： William Robert Alverson , Jerry Anton Ahrens , Anil Harwani , Joshua Taylor Knight , Grant Evan Ley , Amitabh Mehra
IPC: G06F3/06
CPC classification number: G06F3/065 , G06F3/0619 , G06F3/0631 , G06F3/0683
Abstract: Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.
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公开(公告)号：US12038779B2
公开(公告)日：2024-07-16
申请号：US17704684
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Amitabh Mehra , William Robert Alverson , Jerry Anton Ahrens , Grant Evan Ley , Anil Harwani , Joshua Taylor Knight
CPC classification number: G06F1/08 , G06F1/206 , G06F1/305 , G06F1/324 , G06F1/3296
Abstract: User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.
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