公开(公告)号：US20130285113A1

公开(公告)日：2013-10-31

申请号：US13457600

申请日：2012-04-27

申请人： HENRY LITZMANN EDWARDS ,  AKRAM A. SALMAN

发明人： HENRY LITZMANN EDWARDS ,  AKRAM A. SALMAN

IPC分类号： H01L23/60 ,  H01L27/08

CPC分类号： H01L27/0262

摘要： A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

摘要翻译： 双向静电放电（ESD）保护装置包括具有顶侧半导体表面的衬底，其包括第一可控硅整流器（SCR）和形成在其中的第二SCR，其中包括包括多个PBL区域的图案化p埋层（PBL）。 第一SCR包括第一和第二n沟道远程漏极MOS器件，每个具有栅极，p体内的源极和共享第一合流漏极。 第二SCR包括第三和第四n沟道远程漏极MOS器件，每个具有栅极，p体内的源极和共享第二合流漏极。 所述多个PBL区域直接位于所述源的至少一部分之外，而不被排除在所述合并的排水管之下。

公开(公告)号：US08018002B2

公开(公告)日：2011-09-13

申请号：US12490749

申请日：2009-06-24

申请人： Akram A. Salman ,  Stephen G. Beebe ,  Shuqing Cao

发明人： Akram A. Salman ,  Stephen G. Beebe ,  Shuqing Cao

IPC分类号： H01L23/62

CPC分类号： H01L21/84 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

摘要翻译： 提供了一种静电放电保护装置和方法，用于通过在正常（非ESD）操作期间临时形成半导体器件来防止静电放电事件，在位于阳极之间的第一阱区（104）中的两个反转层（112,113） 和阴极区域（105,106），以响应于接近Vdd的一个或多个偏置电压（G1，G2），以便在正常操作（非ESD）状态期间减少漏电流和电容。 在静电放电事件期间，可以去除偏置电压（例如，去耦合或设置为0V）以消除反转层，从而形成用于分流ESD电流的半导体电阻器。

公开(公告)号：US07609493B1

公开(公告)日：2009-10-27

申请号：US11027980

申请日：2005-01-03

申请人： Akram A. Salman ,  Stephen G. Beebe

发明人： Akram A. Salman ,  Stephen G. Beebe

IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22 ,  H01C7/12 ,  H02H1/00 ,  H02H9/06

CPC分类号： H01L27/0255 ,  H01C7/12

摘要： An electrostatic discharge (ESD) protection circuit and a method for reducing capacitance in the ESD protection circuit. A pair of gated diodes are connected in series, wherein the anode of one of the gated diodes is coupled to a lower voltage supply node and the cathode the other gated diode is connected to the upper voltage supply node. The commonly connected anode and cathode of the series connected gated diodes are connected to an input/output pad and to receiver and driver circuitry. The gates of the gated diodes are connected together. A gate biasing circuit is connected to the gates of the gated diodes. The gate biasing circuit applies a voltage to the gates of the gated diodes and depletes their channel regions of charge carriers, which lowers the capacitances of each gate diode.

摘要翻译： 一种静电放电（ESD）保护电路和一种降低ESD保护电路电容的方法。 一对门控二极管串联连接，其中一个门控二极管的阳极耦合到一个较低电压电源节点，另一个栅极二极管连接到上电压供应节点。 串联连接的门控二极管的共同连接的阳极和阴极连接到输入/输出焊盘和接收器和驱动器电路。 门控二极管的栅极连接在一起。 栅极偏置电路连接到门控二极管的栅极。 栅极偏置电路向门控二极管的栅极施加电压，并消耗其电荷载流子的沟道区，这降低了每个栅极二极管的电容。

公开(公告)号：US07560777B1

公开(公告)日：2009-07-14

申请号：US11270029

申请日：2005-11-08

申请人： Akram A. Salman ,  Stephen G. Beebe

发明人： Akram A. Salman ,  Stephen G. Beebe

IPC分类号： H01L23/62

CPC分类号： H01L23/60 ,  H01L27/0255 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (“ESD”) protection circuit having dynamically configurable series-connected diodes and a method for manufacturing the ESD protection circuit. A doped region of P-type conductivity and a doped region of N-type conductivity are formed in an SOI layer of P-type conductivity, wherein the doped regions are laterally spaced apart by a portion of the SOI layer. At least one gate structure is formed on the SOI region that is between the N-type and P-type doped regions. During normal operation, a portion of the SOI region that is adjacent to and between the P-type and N-type doped regions is biased so that it becomes a region of N-type conductivity, thereby forming two series-connected diodes. During an ESD event, the bias is changed so that the region between the P-type and N-type doped regions becomes a region of P-type conductivity, thereby forming a single P-N junction diode.

摘要翻译： 具有可动态配置的串联二极管的静电放电（“ESD”）保护电路和用于制造ESD保护电路的方法。 P型导电性的掺杂区域和N型导电性的掺杂区域形成在P型导电性的SOI层中，其中掺杂区域被SOI层的一部分横向隔开。 在N型和P型掺杂区域之间的SOI区域上形成至少一个栅极结构。 在正常操作期间，与P型和N型掺杂区相邻并且在其之间的SOI区的一部分被偏压，使得其成为N型导电性的区域，由此形成两个串联连接的二极管。 在ESD事件期间，改变偏压，使得P型和N型掺杂区域之间的区域变为P型导电性区域，从而形成单个P-N结二极管。

公开(公告)号：US08704271B2

公开(公告)日：2014-04-22

申请号：US13457600

申请日：2012-04-27

申请人： Henry Litzmann Edwards ,  Akram A. Salman

发明人： Henry Litzmann Edwards ,  Akram A. Salman

IPC分类号： H01L29/66

CPC分类号： H01L27/0262

摘要： A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

摘要翻译： 双向静电放电（ESD）保护装置包括具有顶侧半导体表面的衬底，其包括第一可控硅整流器（SCR）和形成在其中的第二SCR，其中包括包括多个PBL区域的图案化p埋层（PBL）。 第一SCR包括第一和第二n沟道远程漏极MOS器件，每个具有栅极，p体内的源极和共享第一合流漏极。 第二SCR包括第三和第四n沟道远程漏极MOS器件，每个具有栅极，p体内的源极和共享第二合流漏极。 所述多个PBL区域直接位于所述源的至少一部分之外，而不被排除在所述合并的排水管之下。

公开(公告)号：US20130264640A1

公开(公告)日：2013-10-10

申请号：US13441318

申请日：2012-04-06

申请人： AKRAM A. SALMAN ,  FARZAN FARBIZ ,  ARAVIND C. APPASWAMY ,  JOHN ERIC KUNZ, JR. ,  GIANLUCA BOSELLI

发明人： AKRAM A. SALMAN ,  FARZAN FARBIZ ,  ARAVIND C. APPASWAMY ,  JOHN ERIC KUNZ, JR. ,  GIANLUCA BOSELLI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41725 ,  H01L29/0692 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free.

摘要翻译： 形成漏极延伸金属氧化物半导体（MOS）晶体管的方法包括在衬底的半导体表面部分上的栅极电介质上形成包括栅电极的栅极结构。 半导体表面部分具有第一掺杂类型。 源极形成在具有第二掺杂类型的栅极结构的一侧上。 形成漏极，其包括在具有第二掺杂类型的栅极结构的另一侧上的高掺杂部分。 掩模层形成在高掺杂漏极部分的表面区域的第一部分上。 高掺杂漏极部分的表面积的第二部分不具有掩模层。 使用选择性硅化物在第二部分上形成硅化物。 掩模层在第一部分上阻挡硅化物，使得第一部分不含硅化物。

公开(公告)号：US20080247101A1

公开(公告)日：2008-10-09

申请号：US11697859

申请日：2007-04-09

申请人： Akram A. Salman ,  Stephen G. Beebe ,  Mario M. Pelella

发明人： Akram A. Salman ,  Stephen G. Beebe ,  Mario M. Pelella

IPC分类号： H02H9/00 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0288

摘要： An IO buffer is formed having a substrate resistor at a support layer of a semiconductor on insulator substrate. A diode junction is formed between the substrate resistor and portion of the semiconductor on insulator substrate underlying the substrate resistor. In the event of a high-voltage event, current will flow through the diode junction.

摘要翻译： 在绝缘体上半导体衬底的支撑层上形成具有衬底电阻器的IO缓冲器。 在衬底电阻器和衬底电阻器下面的绝缘体上半导体衬底的部分之间形成二极管结。 在高电压事件的情况下，电流将流过二极管结。

公开(公告)号：US09293460B2

公开(公告)日：2016-03-22

申请号：US13594106

申请日：2012-08-24

申请人： Henry Litzmann Edwards ,  Akram A. Salman

发明人： Henry Litzmann Edwards ,  Akram A. Salman

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

摘要： An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

公开(公告)号：US20140054642A1

公开(公告)日：2014-02-27

申请号：US13594106

申请日：2012-08-24

申请人： Henry Litzmann EDWARDS ,  Akram A. SALMAN

发明人： Henry Litzmann EDWARDS ,  Akram A. SALMAN

IPC分类号： H01L27/092 ,  H01L21/265

CPC分类号： H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

摘要： An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

摘要翻译： 集成电路包括NMOS SCR，其中NMOS晶体管的p型体阱为垂直NPN层堆叠提供基极层。 通过使用在基底区域上具有切口掩模元件的注入掩模注入p型掺杂剂来形成基底层，以便从基底区域阻挡p型掺杂剂。 基极层与集成电路中的逻辑元件中NMOS晶体管的p型体阱同时注入。 随后的退火导致p型掺杂剂扩散到基极区域中，形成具有较低掺杂密度的基极，即在NMOS SCR中的NMOS晶体管的主体阱的相邻区域。 NMOS SCR可以具有对称晶体管，漏极延伸晶体管，或者可以是具有与漏极延伸晶体管集成的对称晶体管的双向NMOS SCR。

公开(公告)号：US08310011B2

公开(公告)日：2012-11-13

申请号：US13208610

申请日：2011-08-12

申请人： Akram A. Salman ,  Stephen G. Beebe ,  Shuqing Cao

发明人： Akram A. Salman ,  Stephen G. Beebe ,  Shuqing Cao

IPC分类号： H01L23/62

CPC分类号： H01L21/84 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

摘要翻译： 提供了一种静电放电保护装置和方法，用于通过在正常（非ESD）操作期间临时形成半导体器件来防止静电放电事件，在位于阳极之间的第一阱区（104）中的两个反转层（112,113） 和阴极区域（105,106），以响应于接近Vdd的一个或多个偏置电压（G1，G2），以便在正常操作（非ESD）状态期间减少漏电流和电容。 在静电放电事件期间，可以去除偏置电压（例如，去耦合或设置为0V）以消除反转层，从而形成用于分流ESD电流的半导体电阻器。