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    MINIMIZING BANDWITH TO COMPRESS OUTPUT STREAM IN INSTRUCTION TRACING SYSTEMS
    2.
    发明申请
    MINIMIZING BANDWITH TO COMPRESS OUTPUT STREAM IN INSTRUCTION TRACING SYSTEMS 有权
    在指令跟踪系统中最小化压缩输出流

    公开(公告)号：US20150006868A1

    公开(公告)日：2015-01-01

    申请号：US13930501

    申请日：2013-06-28

    申请人： Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  MD A. Rahman

    发明人： Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  MD A. Rahman

    IPC分类号： G06F9/38

    CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/81

    摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

    摘要翻译： 根据本文公开的实施例，提供了用于最小化带宽以压缩指令跟踪系统的输出流的系统和方法。 例如，该方法可以包括将IT模块的跟踪中的当前指令识别为条件分支（CB）指令。 该方法包括执行以下步骤：生成包括具有CB指令的结果的指示的字节模式的CB分组，或者将CB指令的结果的指示添加到现有CB分组的字节模式。 该方法包括当跟踪中的后续指令不是CB指令时产生分组。 该分组与CB分组不同。 该方法还包括当分组可延迟时将分组添加到延迟队列中。 该方法还包括将后续的延迟分组的CB分组输出到分组日志中。

    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR
    3.
    发明申请
    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR 审中-公开
    在多处理器中基于预测的螺纹选择

    公开(公告)号：US20140201505A1

    公开(公告)日：2014-07-17

    申请号：US13997837

    申请日：2012-03-30

    申请人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    发明人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  Y02D10/24

    摘要： A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.

    摘要翻译： 处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择 在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择 基于预测的当前循环中的第一和第二个线程。