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    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR
    1.
    发明申请
    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR 审中-公开
    在多处理器中基于预测的螺纹选择

    公开(公告)号：US20140201505A1

    公开(公告)日：2014-07-17

    申请号：US13997837

    申请日：2012-03-30

    申请人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    发明人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  Y02D10/24

    摘要： A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.

    摘要翻译： 处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择 在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择 基于预测的当前循环中的第一和第二个线程。

    Mechanism and method to track oldest processor event
    5.
    发明申请
    Mechanism and method to track oldest processor event 失效
    跟踪最旧的处理器事件的机制和方法

    公开(公告)号：US20080148282A1

    公开(公告)日：2008-06-19

    申请号：US11641424

    申请日：2006-12-18

    申请人： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

    发明人： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3865 ,  G06F9/3857

    摘要： Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an out-of-order processor. Dispatched instructions (or micro-ops) may be maintained in a queue, such as a reorder buffer (ROB), for in-order retirement. For at least one embodiment, event information is maintained only in the register and is not maintained in a ROB. For at least one other embodiment, event information is maintained in a ROB entry for some events and in the register for others. For such latter embodiment, a retire engine takes the contents of both the ROB entry and the register into account when determining whether to take an exception or otherwise initiate a handling sequence during in-order instruction retirement. Other embodiments are also described and claimed.

    摘要翻译： 方法，装置和系统实施例提供了一个寄存器来跟踪处理器中最旧的异常事件或粘性事件。 处理器可以是乱序处理器。 调度的指令（或微操作）可以被维护在队列中，例如重新排序缓冲器（ROB），用于按顺序退出。 对于至少一个实施例，事件信息仅在寄存器中被维护，并且不保持在ROB中。 对于至少一个其他实施例，事件信息在一些事件的ROB条目中以及在其他的注册中保持。 对于这样的后一个实施例，退休引擎在确定是否采取异常或在按顺序指令退出时以其他方式启动处理顺序时考虑到ROB入口和寄存器两者的内容。 还描述和要求保护其他实施例。

    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    6.
    发明申请
    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    具有分支机构错误预测的第二个执行单元的处理程序

    公开(公告)号：US20140195790A1

    公开(公告)日：2014-07-10

    申请号：US13994676

    申请日：2011-12-28

    申请人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    发明人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

    摘要翻译： 次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而 初级JEU不处理分支。 此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

    Systems and methods for flag tracking in move elimination operations
    7.
    发明授权
    Systems and methods for flag tracking in move elimination operations 有权
    移动消除操作中标志跟踪的系统和方法

    公开(公告)号：US09292288B2

    公开(公告)日：2016-03-22

    申请号：US13861009

    申请日：2013-04-11

    申请人： Vijaykumar B. Kadgi ,  Jeremy R. Anderson ,  James D. Hadley ,  Tong Li ,  Matthew C. Merten

    发明人： Vijaykumar B. Kadgi ,  Jeremy R. Anderson ,  James D. Hadley ,  Tong Li ,  Matthew C. Merten

    IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/38

    CPC分类号： G06F9/30105 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

    摘要翻译： 涉及移动消除的数据处理操作中标志跟踪的系统和方法。 示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个 位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

    Systems and Methods for Flag Tracking in Move Elimination Operations
    8.
    发明申请
    Systems and Methods for Flag Tracking in Move Elimination Operations 有权
    移动消除操作中标志跟踪的系统和方法

    公开(公告)号：US20140310504A1

    公开(公告)日：2014-10-16

    申请号：US13861009

    申请日：2013-04-11

    申请人： VIJAYKUMAR B. KADGI ,  JEREMY R. ANDERSON ,  JAMES D. HADLEY ,  TONG LI ,  MATTHEW C. MERTEN

    发明人： VIJAYKUMAR B. KADGI ,  JEREMY R. ANDERSON ,  JAMES D. HADLEY ,  TONG LI ,  MATTHEW C. MERTEN

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30105 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

    摘要翻译： 涉及移动消除的数据处理操作中标志跟踪的系统和方法。 示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个 位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

    Tracking an oldest processor event using information stored in a register and queue entry
    9.
    发明授权
    Tracking an oldest processor event using information stored in a register and queue entry 失效
    使用存储在寄存器和队列条目中的信息跟踪最旧的处理器事件

    公开(公告)号：US07721076B2

    公开(公告)日：2010-05-18

    申请号：US11641424

    申请日：2006-12-18

    申请人： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

    发明人： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3865 ,  G06F9/3857

    摘要： Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an out-of-order processor. Dispatched instructions (or micro-ops) may be maintained in a queue, such as a reorder buffer (ROB), for in-order retirement. For at least one embodiment, event information is maintained only in the register and is not maintained in a ROB. For at least one other embodiment, event information is maintained in a ROB entry for some events and in the register for others. For such latter embodiment, a retire engine takes the contents of both the ROB entry and the register into account when determining whether to take an exception or otherwise initiate a handling sequence during in-order instruction retirement. Other embodiments are also described and claimed.

    摘要翻译： 方法，装置和系统实施例提供了一个寄存器来跟踪处理器中最旧的异常事件或粘性事件。 处理器可以是乱序处理器。 调度的指令（或微操作）可以被维护在队列中，例如重新排序缓冲器（ROB），用于按顺序退出。 对于至少一个实施例，事件信息仅在寄存器中被维护，并且不保持在ROB中。 对于至少一个其他实施例，事件信息在一些事件的ROB条目中以及在其他的注册中保持。 对于这样的后一个实施例，退休引擎在确定是否采取异常或在按顺序指令退出时以其他方式启动处理顺序时考虑到ROB入口和寄存器两者的内容。 还描述和要求保护其他实施例。