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    ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION
    2.
    发明申请
    ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
    增强环路检测器驱动逻辑优化

    公开(公告)号：US20140189306A1

    公开(公告)日：2014-07-03

    申请号：US13728273

    申请日：2012-12-27

    申请人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    发明人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

    摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

    摘要翻译： 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

    Enhanced loop streaming detector to drive logic optimization
    3.
    发明授权
    Enhanced loop streaming detector to drive logic optimization 有权
    增强循环流检测器驱动逻辑优化

    公开(公告)号：US09354875B2

    公开(公告)日：2016-05-31

    申请号：US13728273

    申请日：2012-12-27

    申请人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    发明人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

    摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

    摘要翻译： 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

    Scheduler Implementing Dependency Matrix Having Restricted Entries
    4.
    发明申请
    Scheduler Implementing Dependency Matrix Having Restricted Entries 审中-公开
    调度器实现具有限制条目的依赖矩阵

    公开(公告)号：US20140181476A1

    公开(公告)日：2014-06-26

    申请号：US13723684

    申请日：2012-12-21

    申请人： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

    发明人： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3838

    摘要： A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

    摘要翻译： 公开了实现具有限制条目的依赖矩阵的调度器。 本公开的处理装置包括：解码单元，用于对指令进行解码;以及可通信地耦合到解码单元的调度器。 在一个实施例中，调度器被配置为接收解码的指令，确定解码的指令限定为由调度器维护的依赖矩阵中的受限保留站（RS）条目类型的分配，识别依赖矩阵中的RS条目 将所识别的空闲RS条目中的一个分配给依赖矩阵中的解码指令的信息，并且通过解码指令的源依赖性信息更新与所要求的RS条目相对应的依赖矩阵的一行。

    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR
    6.
    发明申请
    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR 审中-公开
    在多处理器中基于预测的螺纹选择

    公开(公告)号：US20140201505A1

    公开(公告)日：2014-07-17

    申请号：US13997837

    申请日：2012-03-30

    申请人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    发明人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  Y02D10/24

    摘要： A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.

    摘要翻译： 处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择 在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择 基于预测的当前循环中的第一和第二个线程。

    System and method for reservation station load dependency matrix
    8.
    发明授权
    System and method for reservation station load dependency matrix 有权
    保留站负载依赖矩阵的系统和方法

    公开(公告)号：US07958336B2

    公开(公告)日：2011-06-07

    申请号：US12164666

    申请日：2008-06-30

    申请人： Sagi Lahav ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    发明人： Sagi Lahav ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

    摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

    摘要翻译： 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。

    Critical section detection and prediction mechanism for hardware lock elision
    9.
    发明授权
    Critical section detection and prediction mechanism for hardware lock elision 有权
    硬件锁定检测的关键部分检测和预测机制

    公开(公告)号：US08190859B2

    公开(公告)日：2012-05-29

    申请号：US11599009

    申请日：2006-11-13

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3865 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/528

    摘要： A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.

    摘要翻译： 这里描述了用于检测锁定指令和锁定释放指令以及预测关键部分的方法和装置。 检测逻辑检测到锁定指令，这可能存在于解码逻辑中。 存储/创建与锁定指令相关联的锁定指令条目。 将要写入后续潜在锁定释放指令的地址位置的地址位置和值与通过锁定指令加载的地址和锁定指令的值负载进行比较。 如果地址和值匹配，则确定锁定释放指令与锁定指令匹配。 预测条目存储对诸如最后指令指针（LIP）的锁定指令的引用，并且如果确定锁定解除指令与锁定相匹配，则在后续检测时将要消除表示锁定指令的关联值 指令。