公开(公告)号：US20100141316A1

公开(公告)日：2010-06-10

申请号：US12630585

申请日：2009-12-03

Applicant: Colin WELTIN-WU ,  Enrico Stefano Temporiti Milani ,  Daniele Baldi

Inventor： Colin WELTIN-WU ,  Enrico Stefano Temporiti Milani ,  Daniele Baldi

IPC: H03L7/06

CPC classification number: H03L7/0991 ,  H03L2207/50

Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.

Abstract translation: 全数字锁相环（ADPLL）产生表示连续时间振荡信号的反馈字。 ADPLL包括被配置为输入连续时间振荡信号和参考信号的时间 - 数字转换器（TDC）。 参考信号是参考时钟信号的函数。 TDC被配置为生成数字字，反馈字是数字字的函数。 ADPLL包括延迟电路，其被配置为用至少一个参考时钟信号和连续时间振荡信号输入并由第一抖动信号控制。

公开(公告)号：US08749421B2

公开(公告)日：2014-06-10

申请号：US13501197

申请日：2010-10-12

Applicant: Mariya Kurchuk ,  Colin Weltin-Wu ,  Yannis Tsividis ,  Dominique Morche ,  David Lachartre

Inventor： Mariya Kurchuk ,  Colin Weltin-Wu ,  Yannis Tsividis ,  Dominique Morche ,  David Lachartre

IPC: H03M1/12

CPC classification number: H03M1/0697 ,  H03M1/0631 ,  H03M1/0854 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/125 ,  H03M1/127 ,  H03M1/361 ,  H03M1/74 ,  H04R25/00

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract translation: 公开了用于连续时间数字信号处理和信号表示的系统，装置和方法。 这包括连续时间模数转换器，其配置为接收模拟信号并将其转换为连续时间数字信号，而不使用时钟或任何类型的采样。 该A / D转换可以包括模拟信号的每级表示和每边缘表示以产生数字信号。 然后可以在连续时间信号处理器中处理数字信号。 连续时间信号表示和处理可以具有这样的优点，即在不适用采样的高频应用中提供滤波器。

公开(公告)号：US20130057423A1

公开(公告)日：2013-03-07

申请号：US13501197

申请日：2010-10-12

Applicant: Mariya Kurchuk ,  Colin Weltin-Wu ,  Yannis Tsividis ,  Dominique Morche ,  David Lachartre

Inventor： Mariya Kurchuk ,  Colin Weltin-Wu ,  Yannis Tsividis ,  Dominique Morche ,  David Lachartre

IPC: H03M1/12

CPC classification number: H03M1/0697 ,  H03M1/0631 ,  H03M1/0854 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/125 ,  H03M1/127 ,  H03M1/361 ,  H03M1/74 ,  H04R25/00

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract translation: 公开了用于连续时间数字信号处理和信号表示的系统，装置和方法。 这包括连续时间模数转换器，其配置为接收模拟信号并将其转换为连续时间数字信号，而不使用时钟或任何类型的采样。 该A / D转换可以包括模拟信号的每级表示和每边缘表示以产生数字信号。 然后可以在连续时间信号处理器中处理数字信号。 连续时间信号表示和处理可以具有这样的优点，即在不适用采样的高频应用中提供滤波器。

公开(公告)号：US07940099B2

公开(公告)日：2011-05-10

申请号：US12630585

申请日：2009-12-03

Applicant: Colin Weltin-Wu ,  Enrico Stefano Temporiti Milani ,  Daniele Baldi

Inventor： Colin Weltin-Wu ,  Enrico Stefano Temporiti Milani ,  Daniele Baldi

IPC: H03L7/06

CPC classification number: H03L7/0991 ,  H03L2207/50

Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.

Abstract translation: 全数字锁相环（ADPLL）产生表示连续时间振荡信号的反馈字。 ADPLL包括被配置为输入连续时间振荡信号和参考信号的时间 - 数字转换器（TDC）。 参考信号是参考时钟信号的函数。 TDC被配置为生成数字字，反馈字是数字字的函数。 ADPLL包括延迟电路，其被配置为用至少一个参考时钟信号和连续时间振荡信号输入并由第一抖动信号控制。