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    Hardware accelerator
    1.
    发明授权
    Hardware accelerator 有权
    硬件加速器

    公开(公告)号：US08020142B2

    公开(公告)日：2011-09-13

    申请号：US11610871

    申请日：2006-12-14

    Applicant: Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    Inventor： Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC: G06F9/44 ,  G06F9/45 ,  G06F7/38

    CPC classification number: G06F9/30014 ,  G06F21/72

    Abstract: A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.

    Abstract translation: 一种用于指令处理的方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位，将所述和加载到第三寄存器并加载进位 位到第三寄存器的最高有效位位置以产生第三操作数，经由移位器单元在第三操作数上执行单位移位以产生移位操作数，并将移位的操作数加载到第四寄存器中，加载最低有效位 从总和到第四寄存器的最高有效位位置以产生第四操作数，经由第四操作数产生第一和第二操作数的最大公约数（GCD），并且至少部分地基于第二操作数生成公钥， GCD。 许多替代方案，变化和修改是可能的。

    Configurable exponent FIFO
    2.
    发明授权
    Configurable exponent FIFO 有权
    可配置指数FIFO

    公开(公告)号：US07912886B2

    公开(公告)日：2011-03-22

    申请号：US11610841

    申请日：2006-12-14

    Applicant: Vinodh Gopal ,  Wajdi Feghali ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    Inventor： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    IPC: G06F7/38 ,  H04K1/00 ,  H04L9/00 ,  H04L9/30

    CPC classification number: G06F7/723

    Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    Abstract translation: 本公开提供了一种用于执行模幂运算的系统和方法。 该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。 该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。 该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Programmable processing unit having multiple scopes
    3.
    发明申请
    Programmable processing unit having multiple scopes 失效
    具有多个示波器的可编程处理单元

    公开(公告)号：US20070174372A1

    公开(公告)日：2007-07-26

    申请号：US11354670

    申请日：2006-02-14

    Applicant: Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    Inventor： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC: G06F15/00

    CPC classification number: G06F21/602

    Abstract: In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

    Abstract translation: 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。

    Cryptographic system component
    4.
    发明申请
    Cryptographic system component 审中-公开
    密码系统组件

    公开(公告)号：US20070157030A1

    公开(公告)日：2007-07-05

    申请号：US11323329

    申请日：2005-12-30

    Applicant: Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

    Inventor： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

    IPC: G06F12/14

    CPC classification number: G06F21/602

    Abstract: In general, in aspect, the disclosure describes a system integrated on a single die that includes a first processor core to receive commands from at least one other processor core to perform at least one specified transformative operation on specified data, multiple processing units to perform transformative operations on data, a shared memory, and logic to transfer data between a one of the set of multiple processing units and the shared memory.

    Abstract translation: 一般来说，在本发明中，本公开描述了集成在单个管芯上的系统，其包括第一处理器核心，用于接收来自至少一个其他处理器核心的命令以对指定数据执行至少一个指定的变换操作，多个处理单元执行变换 对数据的操作，共享存储器和用于在多个处理单元组中的一个处理单元和共享存储器之间传送数据的逻辑。

    APPARATUS AND METHOD FOR GENERATING A GALOIS-FIELD SYNDROME
    6.
    发明申请
    APPARATUS AND METHOD FOR GENERATING A GALOIS-FIELD SYNDROME 失效
    用于产生GALOIS-FIELD SYNDROME的装置和方法

    公开(公告)号：US20080059865A1

    公开(公告)日：2008-03-06

    申请号：US11469222

    申请日：2006-08-31

    Applicant: Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Wajdi Feghali ,  Robert P. Ottavi

    Inventor： Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Wajdi Feghali ,  Robert P. Ottavi

    IPC: G11C29/00

    CPC classification number: G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

    Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    Abstract translation: 本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。 一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间​​输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
    7.
    发明授权
    Sram controller for parallel processor architecture including a read queue and an order queue for handling requests 有权
    用于并行处理器架构的Sram控制器，包括读队列和用于处理请求的订单队列

    公开(公告)号：US07305500B2

    公开(公告)日：2007-12-04

    申请号：US10776702

    申请日：2004-02-10

    Applicant: Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

    Inventor： Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

    IPC: G06F9/46

    CPC classification number: G06F13/1642

    Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

    Abstract translation: 用于随机存取存储器的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。

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