公开(公告)号：US20120083111A1

公开(公告)日：2012-04-05

申请号：US13249505

申请日：2011-09-30

Applicant: Ha-Jin Lim ,  Moon-Han Park ,  Eun-Gon Kim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Ha-Jin Lim ,  Moon-Han Park ,  Eun-Gon Kim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/517 ,  H01L29/518

Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Abstract translation: 提供了制造半导体器件的方法。 在该方法中，在基板上形成包括高k电介质材料的栅极绝缘层。 在栅绝缘层上形成蚀刻停止层。 在蚀刻停止层上形成金属层。 在金属层上形成包括非晶硅的硬掩模。 使用硬掩模作为蚀刻掩模对金属层进行图案化以形成金属层图案。

公开(公告)号：US20120070975A1

公开(公告)日：2012-03-22

申请号：US13228089

申请日：2011-09-08

Applicant: Ha-Jin Lim ,  Moon-Han Park ,  Min-Woo Song ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Ha-Jin Lim ,  Moon-Han Park ,  Min-Woo Song ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/28

CPC classification number: H01L27/10873 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L27/10814 ,  H01L27/10894 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.

Abstract translation: 公开了一种形成具有改善的电特性的玛瑙结构的方法。 在基板上形成栅极绝缘层，在栅极绝缘层上形成金属层。 然后，通过物理气相沉积（PVD）工艺在金属层上形成非晶硅层。 在非晶硅层上形成杂质掺杂多晶硅层。 可以防止在非晶硅层和金属层之间的界面处形成氧化物层。

公开(公告)号：US08013402B2

公开(公告)日：2011-09-06

申请号：US12574912

申请日：2009-10-07

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

IPC: H01L21/02

CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

公开(公告)号：US07767512B2

公开(公告)日：2010-08-03

申请号：US12019449

申请日：2008-01-24

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28026 ,  H01L29/49

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

Abstract translation: 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

公开(公告)号：US07482677B2

公开(公告)日：2009-01-27

申请号：US11339086

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L21/4763

CPC classification number: H01L21/022 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02175 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/11502 ,  H01L27/11521

Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Abstract translation: 在制造电介质结构的方法中，在衬底上形成隧道氧化物层图案之后，在隧道氧化物层上形成浮栅。 在形成包括金属氧化硅和包括金属氮氧化硅的第二电介质层图案的第一电介质层图案之后，在电介质结构上形成控制栅极。 由于介电结构包括至少一个金属氧化硅层和至少一个金属氮氧化硅层，所以介电结构可以具有高介电常数和良好的耐热性。 包括电介质结构的非易失性半导体存储器件可能具有良好的电特性，例如大电容和低漏电流。

公开(公告)号：US20070200160A1

公开(公告)日：2007-08-30

申请号：US11650290

申请日：2007-01-05

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Ha-Jin Lim ,  Mi-Young Yu

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Ha-Jin Lim ,  Mi-Young Yu

IPC: H01L29/94

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes a semiconductor substrate comprising an active area where a first conductive channel is formed, a gate electrode formed on the active area formed on the semiconductor substrate and a gate dielectric layer interposed between the active area and the gate electrode. The semiconductor device further includes a charge generating layer formed along the interface between the active area and the gate dielectric layer on the semiconductor substrate so that fixed charges are generated around the interface.

Abstract translation: 半导体器件包括半导体衬底，其包括形成有第一导电沟道的有源区，形成在形成于半导体衬底上的有源区上的栅电极和介于有源区和栅电极之间的栅介质层。 半导体器件还包括沿着半导体衬底上的有源区和栅介电层之间的界面形成的电荷产生层，从而在界面周围产生固定电荷。

公开(公告)号：US20060244147A1

公开(公告)日：2006-11-02

申请号：US11339086

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L23/48

CPC classification number: H01L21/022 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02175 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/11502 ,  H01L27/11521

Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Abstract translation: 在制造电介质结构的方法中，在衬底上形成隧道氧化物层图案之后，在隧道氧化物层上形成浮栅。 在形成包括金属氧化硅和包括金属氮氧化硅的第二电介质层图案的第一电介质层图案之后，在电介质结构上形成控制栅极。 由于介电结构包括至少一个金属氧化硅层和至少一个金属氮氧化硅层，所以介电结构可以具有高介电常数和良好的耐热性。 包括电介质结构的非易失性半导体存储器件可能具有良好的电特性，例如大电容和低漏电流。

公开(公告)号：US20150206974A1

公开(公告)日：2015-07-23

申请号：US14602660

申请日：2015-01-22

Applicant: Ha-Jin Lim ,  Hyeong-Joon Kim ,  Nae-In Lee

Inventor： Ha-Jin Lim ,  Hyeong-Joon Kim ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/20

CPC classification number: H01L29/66818 ,  H01L21/02241 ,  H01L21/28264 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Abstract translation: 半导体器件包括包含III族元素和V族元素的半导体衬底，以及在半导体衬底上的栅极结构。 半导体衬底包括接触栅极结构的底表面的第一区域和设置在第一区域下方的第二区域。 第一区域中的III族元素的浓度低于第一区域中的V族元素的浓度，并且第二区域中的III族元素的浓度基本上等于第二区域中的第V族元素的浓度 地区。

公开(公告)号：US08673747B2

公开(公告)日：2014-03-18

申请号：US13093097

申请日：2011-04-25

Applicant: Jin-Ho Do ,  Ha-Jin Lim ,  Weon-Hong Kim ,  Hoi-Sung Chung ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Jin-Ho Do ,  Ha-Jin Lim ,  Weon-Hong Kim ,  Hoi-Sung Chung ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/00

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/51 ,  H01L29/513

Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.

Abstract translation: 制造半导体器件的方法包括：在半导体衬底上形成外延层; 在所述外延层上形成具有第一厚度的覆盖层; 以及在氧气氛中氧化所述覆盖层以形成具有第二厚度的第一栅极介电层。

公开(公告)号：US08455345B2

公开(公告)日：2013-06-04

申请号：US13228089

申请日：2011-09-08

Applicant: Ha-Jin Lim ,  Moon-Han Park ,  Min-Woo Song ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Ha-Jin Lim ,  Moon-Han Park ,  Min-Woo Song ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/28

CPC classification number: H01L27/10873 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L27/10814 ,  H01L27/10894 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.

Abstract translation: 公开了一种形成具有改善的电特性的玛瑙结构的方法。 在基板上形成栅极绝缘层，在栅极绝缘层上形成金属层。 然后，通过物理气相沉积（PVD）工艺在金属层上形成非晶硅层。 在非晶硅层上形成杂质掺杂多晶硅层。 可以防止在非晶硅层和金属层之间的界面处形成氧化物层。