公开(公告)号：US5812443A

公开(公告)日：1998-09-22

申请号：US662415

申请日：1996-06-10

Applicant: Woo-Bong Lee ,  Heung-Gee Hong ,  Young-Mo Koo

Inventor： Woo-Bong Lee ,  Heung-Gee Hong ,  Young-Mo Koo

IPC: H01L27/108 ,  G11C11/24

CPC classification number: H01L27/10805 ,  H01L27/10808

Abstract: A memory integrated circuit which is driven with a low power and reduced cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and a common drain region are formed on a semiconductor substrate. Four word lines, each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.

Abstract translation: 以低功率和小区域驱动的存储器集成电路及其制造方法。 在半导体衬底上形成具有四个源极区和公共漏极区的H形的多个有源区。 每个具有不同源的四条字线对应地通过有源区的四个源极区中的每一个，从而形成独立地驱动的四个晶体管。 这四个晶体管被设计成共享一个位线，从而将晶体管的驱动电压降低到+ E，fra 1/4 + EE Vcc。 利用低功率驱动源，在小面积上形成四个晶体管和电容器，从而将电池尺寸减小到33％甚至更多。

公开(公告)号：US09281202B2

公开(公告)日：2016-03-08

申请号：US12604757

申请日：2009-10-23

Applicant: Tae-Ho Choi ,  Jung-Hwan Lee ,  Heung-Gee Hong ,  Jeong-Ho Cho ,  Min-Wan Choo ,  Il-Seok Han

Inventor： Tae-Ho Choi ,  Jung-Hwan Lee ,  Heung-Gee Hong ,  Jeong-Ho Cho ,  Min-Wan Choo ,  Il-Seok Han

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/512 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.

Abstract translation: 非易失性存储单元及其制造方法可以确保稳定的操作可靠性以及减小单元尺寸。 非易失性存储单元包括形成在衬底中的漏极区，形成在衬底中的与漏极区分离的源极区，在漏极区和源极区之间形成在衬底上的浮置栅， 在形成漏极区域的方向上形成衬底，形成在浮置栅极的侧壁上的电介质层以及形成在电介质层上以与浮动栅极的至少一个侧壁重叠的控制栅极。

公开(公告)号：US20100270605A1

公开(公告)日：2010-10-28

申请号：US12604757

申请日：2009-10-23

Applicant: Tae-Ho CHOI ,  Jung-Hwan Lee ,  Heung-Gee Hong ,  Jeong-Ho Cho ,  Min-Wan Choo ,  Il-Seok Han

Inventor： Tae-Ho CHOI ,  Jung-Hwan Lee ,  Heung-Gee Hong ,  Jeong-Ho Cho ,  Min-Wan Choo ,  Il-Seok Han

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/512 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.

Abstract translation: 非易失性存储单元及其制造方法可以确保稳定的操作可靠性以及减小单元尺寸。 非易失性存储单元包括形成在衬底中的漏极区，形成在衬底中的与漏极区分离的源极区，在漏极区和源极区之间形成在衬底上的浮置栅， 在形成漏极区域的方向上形成衬底，形成在浮置栅极的侧壁上的电介质层以及形成在电介质层上以与浮动栅极的至少一个侧壁重叠的控制栅极。

公开(公告)号：US6051461A

公开(公告)日：2000-04-18

申请号：US99157

申请日：1998-06-18

Applicant: Woo-Bong Lee ,  Heung-Gee Hong ,  Young-Mo Koo

Inventor： Woo-Bong Lee ,  Heung-Gee Hong ,  Young-Mo Koo

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10805 ,  H01L27/10808

Abstract: A memory integrated circuit which is driven with a low power and reduced the cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and common drain region are formed on a semiconductor substrate. Four word lines each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line, thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.

Abstract translation: 以低功率驱动并减小单元面积的存储器集成电路及其制造方法。 在半导体衬底上形成具有四个源极区域和公共漏极区域的H形的多个有源区域。 每个具有不同源的四条字线对应地通过有源区的四个源区中的每一个，从而独立地形成驱动的四个晶体管。 这四个晶体管被设计成共享一个位线，从而将晶体管的驱动电压降低到+ E，fra 1/4 + EE Vcc。 利用低功率驱动源，在小面积上形成四个晶体管和电容器，从而将电池尺寸减小到33％甚至更多。

公开(公告)号：US5858590A

公开(公告)日：1999-01-12

申请号：US959961

申请日：1997-10-24

Applicant: O Sung Kwon ,  Doo Hee Lee ,  Hyung Sun Yook ,  Heung Gee Hong ,  Young Mo Goo

Inventor： O Sung Kwon ,  Doo Hee Lee ,  Hyung Sun Yook ,  Heung Gee Hong ,  Young Mo Goo

IPC: G03F7/20 ,  G03F1/00 ,  G03F7/26 ,  H01L21/027 ,  G03C5/00

CPC classification number: G03F7/70625 ,  G03F7/20

Abstract: A method for forming photoresist patterns by performing a photolithograpy process by the unit of a predetermined number of wafers, wherein the photoresist patterns are formed under a condition that an exposure time taken to fore each of the photoresist patterns is predetermined taking into consideration a variation in reflection factor, on the basis of the following equation:Z=X+{(r-a).times.(Y-X)/(.beta.-.alpha.)}where, "T" represents a reference thickness corresponding to a thickness of a photoresist film to be patterned to form a corresponding one of the photoresist patterns, exhibiting a minimum reference factor or a maximum reference factor, "T'" a thickness limit more than the reference thickness (T), ".alpha." a reference reflection factor at the reference thickness (T), ".beta." a reflection factor limit at the thickness limit (T'), "r" a varied reflection factor, "X" a reference exposure time at the reference reflection factor (.alpha.), "Y" an exposure time limit at the reflection factor limit (.beta.), and "Z" the varied exposure time.

Abstract translation: 通过以预定数量的晶片为单位执行光刻处理来形成光致抗蚀剂图案的方法，其中在考虑到每个光致抗蚀剂图案之前的曝光时间是预定的条件下形成光致抗蚀剂图案， 反射因子，基于以下等式：Z = X + {（ra）x（YX）/（β-α）}其中，“T”表示对应于待图案化的光致抗蚀剂膜的厚度的参考厚度 形成对应的一个光致抗蚀剂图案，其具有最小参考因子或最大参考因子，“T”“厚度限制大于参考厚度（T），”α“是参考厚度（T）处的参考反射系数， ，“β”是厚度极限（T'）处的反射因子极限，“r”是反射因子，“X”是参考反射系数（α）时的参考曝光时间，“Y” 反射 因子限制（β）和“Z”变化的曝光时间。