公开(公告)号：US09123739B2

公开(公告)日：2015-09-01

申请号：US13548078

申请日：2012-07-12

申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/737 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US08853666B2

公开(公告)日：2014-10-07

申请号：US12159599

申请日：2006-10-25

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC分类号： H01L29/06 ,  H01L29/15 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

摘要翻译： 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg /a≥5，并且在这种情况下，沟道的层厚度 只要在室温下积聚在通道层中的二维电子气的德布罗意波长，不超过5倍（约500）的范围内选择层。

公开(公告)号：US08689079B2

公开(公告)日：2014-04-01

申请号：US13333345

申请日：2011-12-21

申请人： Yoko Masuo ,  Taichiro Yamanaka ,  Hironobu Miyamoto

发明人： Yoko Masuo ,  Taichiro Yamanaka ,  Hironobu Miyamoto

IPC分类号： H03M13/00

CPC分类号： G06F11/141

摘要： According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.

摘要翻译： 根据一个实施例，命令发生器在预定的访问过程中顺序地并且推测地向存储器接口发送逐个通道访问命令。 如果在通过多个通道的任何存储器访问中发生错误，则清除器使用清除响应返回一系列未执行的已发出的访问命令。 命令进度管理器更新命令进度信息，使得多个通道中的每个通道上的命令进程返回到发布到通道的一系列返回的访问命令的最早访问命令中指定的位置。 命令生成器根据更新的命令进度信息发出逐个通道访问命令，包括对存储器接口的最早访问命令。

公开(公告)号：US08618578B2

公开(公告)日：2013-12-31

申请号：US13147676

申请日：2010-02-03

申请人： Kazuki Ota ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Kazuki Ota ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/4236 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66621 ,  H01L29/7783 ,  H01L29/7787

摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0

摘要翻译： 场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112） ，其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。 所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105） 其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。 氮化物类半导体多层结构中的各层的Al组成满足0

公开(公告)号：US08466495B2

公开(公告)日：2013-06-18

申请号：US13468373

申请日：2012-05-10

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

摘要翻译： 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0 @ y 1）组成的沟道层12; 由Al x Ga 1-x N（0 @ x 1）构成的载流子供给层13，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10×11× NA×eta×t [cm-2] <5.6×1013x，其中x表示载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，eta表示活化 比。

公开(公告)号：US08426895B2

公开(公告)日：2013-04-23

申请号：US12735817

申请日：2009-03-23

申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

IPC分类号： H01L29/205

CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66734

摘要： A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2′) is formed on a substrate (1′). A p-type conductive layer (3′) is formed thereon. A second n-type conductive layer (4′) is formed thereon. On the under surface of the substrate (1′), there is a drain electrode (13′) connected to the first n-type conductive layer (2′). On the upper surface of the substrate (1′), there is a source electrode (11′) in ohmic contact with the second n-type conductive layer (4′), and a gate electrode (12′) in contact with the first n-type conductive layer (2′), p-type conductive layer (3′), the second n-type conductive layer (4′) through an insulation film (21′). The gate electrode (12′) and the source electrode (11′) are alternately arranged. The p-type conductive layer (3′) includes In.

摘要翻译： 提供能够抑制穿通现象发生的半导体器件。 在基板（1'）上形成第一n型导电层（2'）。 在其上形成p型导电层（3'）。 在其上形成第二n型导电层（4'）。 在基板（1'）的下表面上，连接有第一n型导电层（2'）的漏电极（13'）。 在基板（1'）的上表面上存在与第二n型导电层（4'）欧姆接触的源电极（11'）和与第一n型导电层（4'）接触的栅电极（12'） n型导电层（2'），p型导电层（3'），通过绝缘膜（21'）的第二n型导电层（4'）。 栅电极（12'）和源电极（11'）交替排列。 p型导电层（3'）包括In。

公开(公告)号：US08344422B2

公开(公告)日：2013-01-01

申请号：US12810096

申请日：2008-12-25

申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/7781

摘要： A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0≦x≦1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0≦y≦1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.

摘要翻译： 半导体器件包括在应变松弛的状态下由Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）层构成的下阻挡层12，以及由In y Ga 1-y N（0＆lt; nlE; 1）层组成的沟道层13。 y）; 1）设置在下阻挡层12上，具有小于下阻挡层12的带隙的带隙，并且表现出压缩应变。 在沟道层13上经由绝缘膜15形成栅极电极1G，在沟道层13上形成有用作欧姆电极的源电极1S和漏电极1D。绝缘膜15由多晶或非晶构成。

公开(公告)号：US20120228674A1

公开(公告)日：2012-09-13

申请号：US13497557

申请日：2010-06-16

申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.

摘要翻译： 提供能够抑制穿通现象发生的半导体装置。 半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和 栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。 漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分 从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分 栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触 待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷 没有电极。

公开(公告)号：US20120221921A1

公开(公告)日：2012-08-30

申请号：US13333345

申请日：2011-12-21

申请人： Yoko MASUO ,  Taichiro Yamanaka ,  Hironobu Miyamoto

发明人： Yoko MASUO ,  Taichiro Yamanaka ,  Hironobu Miyamoto

IPC分类号： G06F11/08 ,  G06F12/00

CPC分类号： G06F11/141

摘要： According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.

摘要翻译： 根据一个实施例，命令发生器在预定的访问过程中顺序地并且推测地向存储器接口发送逐个通道访问命令。 如果在通过多个通道的任何存储器访问中发生错误，则清除器使用清除响应返回一系列未执行的已发出的访问命令。 命令进度管理器更新命令进度信息，使得多个通道中的每个通道上的命令进程返回到发布到通道的一系列返回的访问命令的最早访问命令中指定的位置。 命令生成器根据更新的命令进度信息发出逐个通道访问命令，包括对存储器接口的最早访问命令。

公开(公告)号：US20110284865A1

公开(公告)日：2011-11-24

申请号：US13141449

申请日：2009-12-25

申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。