公开(公告)号：US09224356B2

公开(公告)日：2015-12-29

申请号：US14002948

申请日：2012-03-01

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/00 ,  G09G5/00 ,  H03M1/66 ,  G09G3/32 ,  G09G3/36 ,  H03M1/76

CPC分类号： G09G5/003 ,  G09G3/3291 ,  G09G3/3688 ,  G09G3/3696 ,  G09G5/00 ,  G09G2310/027 ,  G09G2310/0291 ,  H03M1/661 ,  H03M1/76

摘要： DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2^n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A−1+2^n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A−4+2^n) and (A+2^n), and an at most {−4+2^(n−2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {−3+2^(n−2)} reference voltages that are other than the four number of reference voltages from the {1+2^(n−2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2^(n−2).

摘要翻译： DAC包括接收N个参考电压的解码器和用于选择第一至第三电压的n位数字信号（n4），以及输出（第一电压+第二电压+2第三电压）/ 4电压的运算放大器。 对于n位数字信号的相应2 ^ n组合，运算放大器能够从作为基准电平的Ath电平到（A-1 + 2 ^ n）级的电压电平输出。 N个参考电压包括Ath电平，（A + 4）电平，（A-4 + 2 ^ n）和（A + 2 ^ n），以及至多{-4 + 2 ^（n-2） ）}参考电压，其通过从{1 + 2 ^（n-2）}个参考电压除去来自{1 + 2 ^（n-2）}的四个参考电压以外的预设的至少一个参考电压而获得 -2）}相对应的电压电平的参考电压以与Ath级别成4级的间隔彼此隔开。 N不小于4且不大于2 ^（n-2）。

公开(公告)号：US08786479B2

公开(公告)日：2014-07-22

申请号：US13064354

申请日：2011-03-21

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/68

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2330/028

摘要： Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal. An interpolation circuit receives the first and second voltages, selected by the decoder, to output a voltage level obtained on interpolation with an interpolation ratio of 1:1 (FIG. 1).

摘要翻译： 参考电压集合的参考电压被分类为第一至第（z×S + 1）个参考电压组，其中S是2的功率，包括1，z是2加1的功率。解码器包括首先（ 和第（z×S + 1）个输入型子解码器相关联地设置的z×S + 1个子解码器。 第一至第（Z×S + 1）子解码器从第一至第（z×S + 1）个参考电压组的参考电压中选择分配给二维阵列中的列的参考电压 与输入数字信号的第一位组的值相关联的参考电压。 （z×S + 1）输入和2输出子解码器接收第一至第（Z×S + 1）个子解码器的输出，以从由第一至第（z） ×S + 1）个子解码器，响应于输入数字信号的第二位组的值。 接收由解码器选择的第一和第二电压的插值电路，以1：1（图1）的插值比率输出以内插获得的电压电平。

公开(公告)号：US08686987B2

公开(公告)日：2014-04-01

申请号：US13029888

申请日：2011-02-17

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0291 ,  G09G2320/0252 ,  G09G2330/021

摘要： Disclosed is an output circuit including a differential amplifier stage, an output amplifier stage, an amplification acceleration circuit and a capacitance connection control circuit. The output amplifier stage includes push/pull type transistors connected an output terminal. The amplification acceleration circuit includes a first switch and a first transistor, connected between a first output of the differential amplifier stage and the output terminal, and a second transistor and a second switch connected between the output terminal and a second output of the differential amplifier stage. The capacitance connection control circuit includes first capacitive element having first end connected to the output terminal, a first switch connected between a second end of the first capacitive element and a first voltage supply terminal, and a second switch connected between the second end of the first capacitive element and one output of a first differential pair of the differential amplifier stage.

摘要翻译： 公开了一种包括差分放大级，输出放大级，放大加速电路和电容连接控制电路的输出电路。 输出放大级包括连接有输出端的推/拉型晶体管。 放大加速电路包括连接在差分放大器级的第一输出端和输出端子之间的第一开关和第一晶体管，以及连接在差分放大器级的输出端子和第二输出端之间的第二晶体管和第二开关 。 电容连接控制电路包括第一电容元件，第一电容元件具有连接到输出端子的第一端子，连接在第一电容元件的第二端和第一电压供应端子之间的第一开关和连接在第一电容元件的第二端之间的第二开关 电容元件和差分放大器级的第一差分对的一个输出。

公开(公告)号：US20130088473A1

公开(公告)日：2013-04-11

申请号：US13612671

申请日：2012-09-12

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00 ,  H03F3/45

CPC分类号： G09G3/3291 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2310/0291 ,  H03F3/3022 ,  H03F3/45076 ,  H03F3/45085 ,  H03F2200/153 ,  H03F2200/78 ,  H03F2203/45116 ,  H03F2203/45506 ,  H03F2203/45646 ,  H03F2203/45648 ,  H03F2203/45726

摘要： An output circuit is capable of supporting a high-speed operation, suppressing power consumption, and controlling its area. The output circuit has a differential input stage, an output amplification stage, and an amplification boost circuit, in which the amplification boost circuit has a differential pair of a second conductivity type and load element pair, and includes a first current source circuit for controlling current supply to an input node of a second current mirror circuit of the differential input stage and boost the charging operation of the output amplification stage according to a voltage difference between input and output voltages, and a second current source circuit for controlling current supply to an output node of a first current mirror circuit of the differential input stage and boost the discharging operation of the output amplification stage.

摘要翻译： 输出电路能够支持高速操作，抑制功耗，并控制其面积。 输出电路具有差分输入级，输出放大级和放大升压电路，其中放大升压电路具有第二导电类型和负载元件对的差分对，并且包括用于控制电流的第一电流源电路 提供给差分输入级的第二电流镜像电路的输入节点，并且根据输入和输出电压之间的电压差升高输出放大级的充电操作;以及第二电流源电路，用于控制对输出的电流供应 节点，并且对输出放大级的放电操作进行升压。

公开(公告)号：US08400207B2

公开(公告)日：2013-03-19

申请号：US12847339

申请日：2010-07-30

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03L5/00

CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2310/0289 ,  H03K19/018521

摘要： A level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V1) when conducting, a second circuit connected between a second PST and OT to set OT to the second voltage (V2) when conducting, and a third circuit that receives an input signal and a feedback signal from OT so that, when OT=V2 and input=a third voltage (V3), the first circuit conducts, and when OT=V1, the first circuit is made nonconductive irrespective of the value of the input signal. The second circuit is made conductive and nonconductive, when the input=a fourth voltage (V4) and V3, respectively. A high/low relationship of V1, V2=that of V3, V4. The input between V3, V4 has a lower amplitude than the output signal between V1, V2.

摘要翻译： 电平移位电路包括连接在电平移位电路的第一电源端子（PST）和输出端子（OT）之间的第一电路，用于在导通时将OT设置为第一电压（V1），第二电路连接在第二电源 PST和OT将OT设置为第二电压（V2）;以及第三电路，其从OT接收输入信号和反馈信号，使得当OT = V2和输入=第三电压（V3）时，第一电路 电路导通，并且当OT = V1时，不管输入信号的值如何，第一电路都是不导通的。 当输入分别为第四电压（V4）和V3时，第二电路导通和不导通。 V1，V2的高低关系为V3，V4。 V3，V4之间的输入幅度比V1，V2之间的输出信号低。

公开(公告)号：US20120146988A1

公开(公告)日：2012-06-14

申请号：US13304433

申请日：2011-11-25

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00 ,  H03L5/00

CPC分类号： G09G3/3696 ,  G09G3/3258 ,  G09G5/00 ,  G09G2310/027 ,  G09G2310/0289 ,  H03K3/356165 ,  H03K19/0175

摘要： A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

摘要翻译： 电平移位电路包括分别耦合在第一电源端子和第一和第二输出节点之间的第一和第二NMOS晶体管，并且各自的控制端子接收低振幅，第三和第四PMOS晶体管的输入信号， 第二供电端子，以及分别输出高幅度信号的第一和第二输出节点，耦合在第三PMOS晶体管的栅极和第二输出节点之间的第五PMOS晶体管，并且具有耦合到第一输出端的栅极 节点，第六PMOS晶体管，其耦合在第四PMOS晶体管的栅极和第一输出节点之间，并且具有耦合到第二输出节点的栅极;以及耦合在第二供电端子和第二PMOS晶体管之间的第一和第二负载元件， 第三和第四PMOS晶体管的栅极。

公开(公告)号：US20110205218A1

公开(公告)日：2011-08-25

申请号：US13027450

申请日：2011-02-15

申请人： Hiroshi TSUCHI ,  Nobuyasu Doi

发明人： Hiroshi TSUCHI ,  Nobuyasu Doi

IPC分类号： G09G5/00 ,  H03K5/22

CPC分类号： G09G3/3688 ,  G09G3/3283 ,  G09G3/3291 ,  G09G2310/027

摘要： Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage. The first power supply voltage is a first reference voltage, which is a most spaced from the second voltage section among the first reference voltage group, or a predetermined voltage even further spaced from the second voltage section than the first reference voltage. The second power supply voltage is a predetermined voltage within a range from a second reference voltage, which is a voltage closest to the first voltage section among the second reference voltage group, to a voltage within the first voltage section but not reaching the first reference voltage.

摘要翻译： 公开了一种解码器，接收第一和第二参考电压组并根据接收到的数字信号选择参考电压，包括接收第一参考电压组的第一子解码器，接收第二参考电压的第二子解码器 并且第三子解码器接收由第二子解码器选择的参考电压，并将所选择的参考电压输出到解码器的第一子解码器或输出端。 第一子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管，第二子解码器包括具有提供有第二电源电压的背栅的第一导电类型的晶体管， 并且第三子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管。 第一电源电压是与第一参考电压组中的第二电压部分最多隔开的第一参考电压或者与第二电压部分比第一参考电压更远的预定电压。 第二电源电压是从第二参考电压组中最接近第一电压部分的电压的第二参考电压到第一电压部分内的电压但没有达到第一参考电压的范围内的预定电压 。

公开(公告)号：US07872499B2

公开(公告)日：2011-01-18

申请号：US12320778

申请日：2009-02-04

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03K19/0175 ,  H03L5/00

CPC分类号： H03K19/018521 ,  G09G3/20 ,  G09G3/3208 ,  G09G3/3611 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/01707

摘要： Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level. When the input signal supplied in the predetermined time interval assumes a value that sets the output terminal to the second voltage level, the second level shifter sets the output terminal to the second voltage level with the first level shifter deactivated.

摘要翻译： 公开了一种电平移位电路，其包括第一电平移位器，其连接在输出端子和提供第一电压的第一电源端子之间，并且当在输入端接收的输入信号时将输出端子设置为第一电压的电平 终端假设第一个值; 第二电平移位器，连接在输出端和提供第二电压的第二电源端之间，当输入信号呈现第一值的互补值时，将输出端设置为第二电压的电平; 以及反馈控制单元，其在包括当检测到在输入端子处接收到输入信号之前的输出端子被假定时提供输入信号的时间点的预定时间间隔期间，执行停用第一电平移位器的控制， 第一个电压电平。 当在预定时间间隔内提供的输入信号采取将输出端子设置为第二电压电平的值时，第二电平移位器将第一电平移位器的输出端子设置为第二电压电平。

公开(公告)号：US07812752B2

公开(公告)日：2010-10-12

申请号：US12289266

申请日：2008-10-23

申请人： Hiroshi Tsuchi ,  Noboru Okuzono

发明人： Hiroshi Tsuchi ,  Noboru Okuzono

IPC分类号： H03M1/66

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  H03M1/661 ,  H03M1/68 ,  H03M1/76

摘要： A digital-to-analog converter circuit includes: a first subdecoder for receiving a first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving a second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving a third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages that have been selected by respective ones of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting a result of an operation applied to the two reference voltages.

摘要翻译： 数模转换器电路包括：第一子编码器，用于接收第一参考电压组并基于输入数字信号选择参考电压Vrk; 第二子编码器，用于接收第二参考电压组，并且基于所输入的数字信号选择参考电压Vr（k + 1）; 第三子编码器，用于接收第三参考电压组，并且基于所输入的数字信号选择参考电压Vr（k + 2）; 第四子编码器，用于接收由第一至第三子解码器中的相应的子编码器选择的参考电压，基于输入的数字信号选择这些参考电压中的两个（包括冗余选择相同的电压），并输出所选择的两个参考 电压; 以及放大器电路，用于接收由第四子解码器选择的两个参考电压并输出施加于两个参考电压的操作结果。

公开(公告)号：US20100052966A1

公开(公告)日：2010-03-04

申请号：US12616459

申请日：2009-11-11

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/78

CPC分类号： H03F3/45179 ,  H03F2203/45504 ,  H03F2203/45521 ,  H03F2203/45616

摘要： Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively. The differential amplifier further includes a load circuit connected to output pairs of the first and second differential pairs for outputting a signal obtained on combining outputs of the first and second differential pairs from at least one of a pair of connection nodes between the output pairs of the first and second differential pairs and the load circuit, an amplifier stage supplied with at least one signal at a connection node of the output pairs of the first and second differential pairs and the load circuit to output a voltage at the output terminal, and a current control circuit controlling the first and second current sources for controlling the ratio of currents supplied to the first and second differential pairs.

摘要翻译： 公开了一种差分放大器，其包括第一和第二输入端子，输出端子，第一和第二差分对以及用于向第一和第二差分对提供电流的第一和第二电流源。 第一差分对具有分别连接到第一输入端和输出端的输入对的第一和第二输入。 第二差分对分别具有连接到第二输入端子和输出端子的输入对的第一和第二输入端。 所述差分放大器还包括连接到所述第一和第二差分对的输出对的负载电路，用于输出在所述第一和第二差分对的输出对之间的一对连接节点中的至少一个上组合所述第一和第二差分对的输出而获得的信号 第一和第二差分对和负载电路，在第一和第二差分对的输出对和负载电路的连接节点处提供至少一个信号的放大器级，以在输出端输出电压，以及电流 控制电路控制第一和第二电流源，以控制提供给第一和第二差分对的电流比。