Abstract:
Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.
Abstract:
Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.
Abstract:
A storage device including a processor to transmit N pages of data from one or more pages in a buffer memory where N is a natural number. The storage device also includes a flash memory to program in parallel the N pages of data to N flash chips. The N pages may be transmitted via one or more channels.
Abstract:
A context switch method capable of promptly switching a context for a dynamically generated task and a dynamic link by converting a state of multiple register files, switching the context, and separately restoring and storing the context. That is, the context switch method includes: maintaining a multiple register files; establishing the multiple register to be in any one of a prefetch state, a current state, and a store state; converting a state of the multiple register files to be in any one of the prefetch state, the current state, and the store state when a context switch occurs; wherein, in the prefetch state, determining a memory address to read a next task context to be subsequently performed by the register file, in the current state, performing a task with the task context of the register file and in the store state, storing the register file in a memory.
Abstract:
An apparatus for managing memory in a real-time embedded system and a method of allocating, deallocating and managing memory in a real-time embedded system. The apparatus includes a defragmentation unit performing a defragmentation task according to a predetermined priority to collect together memory fragments, and a memory manager allocating or deallocating a predetermined area of memory upon request of a task, and calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task. The method of managing memory in a real-time embedded system includes determining whether the conditions under which the memory is used vary, and if the condition vary, calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task according to the memory fragmentation rate.
Abstract:
Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor.
Abstract:
A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.
Abstract:
A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.
Abstract:
The present invention relates a process of quality examining for microarray of biological material. More particularly, the present invention is directed to a process of quality examining for microarray of biological material, which comprises 1) a step for mixing probe and a compound which emits light or heat and does not react with said probe, 2) a step for microarraying the mixture obtained in step 1) on a substrate, and 3) a step for measuring light or heat emitted by the scanning of each spots of the microarray mixture.
Abstract:
Provided are a multitasking method and apparatus. By continuously maintaining the intrinsic information of each peripheral processing unit of when a process-centered task is stopped, when a reconfigurable array stops executing the process-centered task and executes a different process-centered task, by stopping executing a control-centered task and executing a reconfiguration task, only when the reconfigurable array receives an execution request of the reconfiguration task while the reconfigurable array is performing the control-centered task, or by causing a predetermined number of processing units to execute each of a plurality of reconfiguration tasks that are to be simultaneously executed by the reconfigurable array, wherein the predetermined number of processing units is set in consideration of an expected data processing amount required for the reconfiguration task, the reconfigurable array can more quickly complete execution of multitasking.