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公开(公告)号：US20110058426A1
公开(公告)日：2011-03-10
申请号：US12944358
申请日：2010-11-11
IPC分类号： G11C16/06
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US07411834B2
公开(公告)日：2008-08-12
申请号：US11701404
申请日：2007-02-02
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
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公开(公告)号：US08085598B2
公开(公告)日：2011-12-27
申请号：US12944358
申请日：2010-11-11
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US07859909B2
公开(公告)日：2010-12-28
申请号：US12546062
申请日：2009-08-24
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US20090310410A1
公开(公告)日：2009-12-17
申请号：US12546062
申请日：2009-08-24
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US07596033B2
公开(公告)日：2009-09-29
申请号：US12216489
申请日：2008-07-07
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US20080273396A1
公开(公告)日：2008-11-06
申请号：US12216489
申请日：2008-07-07
IPC分类号： G11C16/04
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US20070183213A1
公开(公告)日：2007-08-09
申请号：US11701404
申请日：2007-02-02
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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