公开(公告)号：US5590285A

公开(公告)日：1996-12-31

申请号：US513167

申请日：1995-08-09

申请人： Jeffrey Krause ,  Niles E. Strohl ,  Michael J. Seaman ,  Steven P. Russell ,  John H. Hart

发明人： Jeffrey Krause ,  Niles E. Strohl ,  Michael J. Seaman ,  Steven P. Russell ,  John H. Hart

IPC分类号： G06F13/374 ,  G06F13/00 ,  G06F13/376 ,  H04L12/46 ,  H04L29/06

CPC分类号： H04L12/4625 ,  H04L29/06 ,  H04L45/742 ,  H04L69/18

摘要： DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.

摘要翻译： DLL设备构建有多个MAC地址而不是单个MAC地址，并且在计算机中向上层（3-7）提供多个虚拟DLL接口。 这导致了一类新的多功能计算机，用于连接到利用多个虚拟DLL接口的网络系统，以提高计算机执行的相应功能的性能。 因此，提供了一种新的网络接口控制装置和用于附接到网络的新类型的多功能计算机系统。 介质访问控制装置中的存储器除了分配的网络地址之外还存储多个附加网络地址。 地址过滤逻辑包括响应于附加网络地址的电路，例如当在存储在所述多个数据信道中的附加地址中找到特定帧的源和目的地址时，用于阻塞所述多个数据信道中的至少一个上的特定帧的逻辑 记忆。 由媒体访问控制设备服务的多个数据信道可以驻留在单个物理接口上，或者在独立的物理接口中，以适应特定设计的需要。 高性能设计将包括每个数据通道的独立缓冲和排队结构。 替代设计可以包括用于连接的计算机中具有独立侧网络地址的多个功能模块的共享缓冲和排队结构。

公开(公告)号：US5428766A

公开(公告)日：1995-06-27

申请号：US983907

申请日：1992-12-01

申请人： Michael J. Seaman

发明人： Michael J. Seaman

IPC分类号： G06F11/00 ,  G06F11/34

CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/349

摘要： An error detection scheme to detect a variety of errors, including buffer accesses errors, buffer ownership transfer errors, and address recognition engine access errors, that may occur during the passing of messages between processors in a multi-processor computer system implementing a buffer swapping scheme. The error detection scheme of the present invention provides for the monitoring of bus transactions, maintaining a log of bus activity including buffer access transactions, identifying transactions involving buffer and address recognition operations and checking those operations to insure that they are consistent with the implemented buffer swapping scheme. Upon detection of an error the bus monitoring device asserts an error signal, freezes the log of bus activity and halts buffer swapping activity until the detected error is investigated and dealt with in an appropriate manner.

摘要翻译： 用于检测在执行缓冲器交换方案的多处理器计算机系统中的处理器之间的消息传递期间可能发生的各种错误的错误检测方案，包括缓冲器访问错误，缓冲器所有权转移错误和地址识别引擎访问错误 。 本发明的错误检测方案提供了对总线事务的监视，维护包括缓冲器访问事务的总线活动记录，识别涉及缓冲器和地址识别操作的事务，并检查这些操作以确保它们与实现的缓冲器交换一致 方案。 在检测到错误时，总线监控设备断言错误信号，冻结总线活动的日志并停止缓冲区交换活动，直到检测到的错误被调查并以适当的方式处理。

公开(公告)号：US5202999A

公开(公告)日：1993-04-13

申请号：US819186

申请日：1992-01-10

申请人： John M. Lenthall ,  Neal A. Crook ,  Helen C. McGreal ,  Michael J. Seaman

发明人： John M. Lenthall ,  Neal A. Crook ,  Helen C. McGreal ,  Michael J. Seaman

IPC分类号： G06F13/37

CPC分类号： G06F13/37

摘要： An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks. When certain preselected highest priority determination conditions occur within one of the combinational logic blocks, the combinational logic block generates a token signal which serves as the token signal to the respective succeeding combinational logic block. Each combinational logic block is capable of receiving a token signal from the previous combinational logic block and is responsive to the input of a token signal to determine a current highest priority from the values which it received as input signals.

摘要翻译： 用于确定n个实体当前最高优先级的访问请求优先级和摘要设备。 该设备包括具有n位存储位置的位图。 n位存储位置中的每一个对应于一个实体，并且用于存储表示当对应实体可用于优先化的时间的值。 多个组合逻辑块连接到位图，使得组合逻辑块中的每一个接收存储在位图的n位存储位置中的值的预选部分。 组合逻辑块中的每一个具有令牌信号输入和令牌信号输出。 令牌信号输入和输出耦合在一起以在组合逻辑块之间形成一系列令牌信号链路。 当在组合逻辑块之一内发生某些预选的最高优先级确定条件时，组合逻辑块产生令牌信号，令牌信号用作相应的后续组合逻辑块的令牌信号。 每个组合逻辑块能够从先前的组合逻辑块接收令牌信号，并响应于令牌信号的输入，以从作为输入信号接收的值确定当前最高优先级。

公开(公告)号：US5644571A

公开(公告)日：1997-07-01

申请号：US73217

申请日：1993-06-04

申请人： Michael J. Seaman

发明人： Michael J. Seaman

IPC分类号： H04L12/46 ,  H04J3/02

CPC分类号： H04L12/4625

摘要： In an apparatus in a computer network, message filtering proceeds by generating respective class specifiers from a received message, using the message source field, message destination field, and type of message field. The class specifiers are used for generating a class specification, and a domain class is generated from the class specification. A domain list is generated to provide a list of ports to which a message directed to the domain class is to be forwarded. The message is forwarded to the ports listed in the domain list. The apparatus may be a bridge, router, etc.

摘要翻译： 在计算机网络中的装置中，消息过滤通过使用消息源字段，消息目的地字段和消息字段的类型从接收的消息生成相应的类说明符来进行。 类说明符用于生成类规范，并且从类规范生成域类。 生成域列表以提供要转发到域类的消息的端口列表。 该消息将转发到域列表中列出的端口。 设备可以是桥接器，路由器等

公开(公告)号：US5535338A

公开(公告)日：1996-07-09

申请号：US452498

申请日：1995-05-30

申请人： Jeffrey Krause ,  Niles E. Strohl ,  Michael J. Seaman ,  Steven P. Russell ,  John H. Hart

发明人： Jeffrey Krause ,  Niles E. Strohl ,  Michael J. Seaman ,  Steven P. Russell ,  John H. Hart

IPC分类号： G06F13/374 ,  G06F13/00 ,  G06F13/376 ,  H04L12/46 ,  H04L29/06

CPC分类号： H04L12/4625 ,  H04L29/06 ,  H04L45/742 ,  H04L69/18

摘要： DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.

摘要翻译： DLL设备构建有多个MAC地址而不是单个MAC地址，并且在计算机中向上层（3-7）提供多个虚拟DLL接口。 这导致了一类新的多功能计算机，用于连接到利用多个虚拟DLL接口的网络系统，以提高计算机执行的相应功能的性能。 因此，提供了一种新的网络接口控制装置和用于附接到网络的新类型的多功能计算机系统。 介质访问控制装置中的存储器除了分配的网络地址之外还存储多个附加网络地址。 地址过滤逻辑包括响应于附加网络地址的电路，例如当在存储在所述多个数据信道中的附加地址中找到特定帧的源和目的地址时，用于阻塞所述多个数据信道中的至少一个上的特定帧的逻辑 记忆。 由媒体访问控制设备服务的多个数据信道可以驻留在单个物理接口上，或者在独立的物理接口中，以适应特定设计的需要。 高性能设计将包括每个数据通道的独立缓冲和排队结构。 替代设计可以包括用于连接的计算机中具有独立侧网络地址的多个功能模块的共享缓冲和排队结构。

公开(公告)号：US5526489A

公开(公告)日：1996-06-11

申请号：US33914

申请日：1993-03-19

申请人： Chandrasekharan Nilakantan ,  Ly Loi ,  Nagaraj Arunkumar ,  Michael J. Seaman

发明人： Chandrasekharan Nilakantan ,  Ly Loi ,  Nagaraj Arunkumar ,  Michael J. Seaman

IPC分类号： G06F13/00 ,  H04L12/46 ,  H04L12/66 ,  H04L12/931 ,  H04L29/06 ,  H04L29/12 ,  G06F15/16 ,  G06F15/163 ,  G06F15/177

CPC分类号： H04L29/12018 ,  H04L29/06 ,  H04L29/12009 ,  H04L49/351 ,  H04L61/10

摘要： A reverse address resolution protocol for use in a communication network which allows resolution logic to provide a higher level protocol information (such as an IP address) to a source of a request for such information, independent of the physical network address of such source. The protocol is used in a processor having a plurality of ports, at least one of such ports connected by a point-to-point channel to a remote network device. Reverse address resolution protocol is responsive to a resolution request from the remote network device across the point-to-point channel to supply the higher level protocol information based upon the port through which the resolution request is received, rather than the physical network address of the requesting device. Thus, a remote device may be coupled to a network, and connected to a central management site across a point-to-point communication link, in a "plug and play" mode. The person connecting the device to the remote network does not need to determine the physical network address of the device or configure the device with a higher level address protocol.

摘要翻译： 一种在通信网络中使用的反向地址解析协议，其允许分辨率逻辑向这种信息的请求的源提供更高级别的协议信息（诸如IP地址），而与该源的物理网络地址无关。 该协议用于具有多个端口的处理器中，至少一个这样的端口通过点到点信道连接到远程网络设备。 反向地址解析协议响应来自远程网络设备的跨点对点信道的解析请求，以便基于接收到解析请求的端口而不是接收到的物理网络地址来提供更高级协议信息 请求设备。 因此，远程设备可以耦合到网络，并且以“即插即用”模式通过点对点通信链路连接到中央管理站点。 将设备连接到远程网络的人不需要确定设备的物理网络地址或配置具有较高级别地址协议的设备。

公开(公告)号：US5524254A

公开(公告)日：1996-06-04

申请号：US269997

申请日：1994-07-01

申请人： Fearghal Morgan ,  Joseph O'Callaghan ,  Michael J. Seaman ,  John Rigby ,  Andrew Walton ,  Una M. Quinlan ,  Stewart F. Bryant

发明人： Fearghal Morgan ,  Joseph O'Callaghan ,  Michael J. Seaman ,  John Rigby ,  Andrew Walton ,  Una M. Quinlan ,  Stewart F. Bryant

IPC分类号： G06F13/00 ,  H04L12/46 ,  H04L29/06 ,  H04L29/12

CPC分类号： H04L29/12801 ,  H04L12/46 ,  H04L29/12009 ,  H04L29/12839 ,  H04L45/742 ,  H04L61/6004 ,  H04L61/6022 ,  H04L69/18 ,  H04L69/22

摘要： The present invention provides an interlock scheme for use between a line card and an address recognition apparatus. The interlock scheme reduces the total number of read/write operations over a backplane bus coupling the line card to the address recognition apparatus required to complete a request/response transfer. Thus, the line card and address recognition apparatus are able to perform a large amount of request/response transfers with a high level of system efficiency. Generally, the interlocking scheme according to the present invention merges each ownership information storage location into the location of the request/response memory utilized to store the corresponding request/response pair to reduce data transfer traffic over the backplane bus. According to another feature of the interlock scheme of the present invention, each of the line card and the address recognition engine includes a table for storing information relating to a plurality of database specifiers. Each of the database specifiers contains control information for the traversal of a lookup database used by the address recognition apparatus. At the time the processor of a line card generates a request for the address recognition apparatus, it will analyze the protocol type information contained in the header of a data packet. The processor will utilize the protocol type information as a look-up index to its table of database specifiers for selection of one of the database specifiers. The processor will then insert an identification of the selected database specifier into the request with the network address extracted from the data packet.

摘要翻译： 本发明提供了一种用于线卡和地址识别装置之间的互锁方案。 互锁方案减少了通过将线卡耦合到完成请求/响应传输所需的地址识别装置的背板总线上的读/写操作的总数。 因此，线卡和地址识别装置能够以高水平的系统效率执行大量的请求/响应传送。 通常，根据本发明的联锁方案将每个所有权信息存储位置合并到用于存储相应的请求/响应对的请求/响应存储器的位置，以减少背板总线上的数据传输流量。 根据本发明的联锁方案的另一特征，线卡和地址识别引擎中的每一个都包括用于存储与多个数据库说明符有关的信息的表。 每个数据库说明符包含用于遍历由地址识别装置使用的查找数据库的控制信息。 当线卡的处理器产生对地址识别装置的请求时，它将分析包含在数据分组头部中的协议类型信息。 处理器将利用协议类型信息作为其数据库说明符表的查找索引，以选择其中一个数据库说明符。 然后处理器将所选择的数据库说明符的标识插入到从数据包中提取的网络地址的请求中。

公开(公告)号：US5519858A

公开(公告)日：1996-05-21

申请号：US819490

申请日：1992-01-10

申请人： Andrew Walton ,  Una M. Quinlan ,  Stewart F. Bryant ,  Michael J. Seaman ,  John Rigby ,  Fearghal Morgan ,  Joseph O'Callaghan

发明人： Andrew Walton ,  Una M. Quinlan ,  Stewart F. Bryant ,  Michael J. Seaman ,  John Rigby ,  Fearghal Morgan ,  Joseph O'Callaghan

IPC分类号： G06F17/30 ,  H04L12/56 ,  H04L29/06

CPC分类号： H04L29/06

摘要： The present invention is directed to an address recognition apparatus including an address recognition engine coupled to a look-up database. The look-up database is arranged to store network information relating to network addresses. The look-up database includes a primary database and a secondary database. The address recognition engine accepts as an input a network address for which network information is required. The address recognition engine uses the network address as an index to the primary database. The primary database comprises a multiway tree node structure (TRIE) arranged for traversal of the nodes as a function of preselected segments of the network address and in a fixed sequence of the segments to locate a pointer to an entry in the secondary database. The entry in the secondary database pointed to by the primary database pointer contains the network information corresponding to the network address. The address recognition engine includes a table for storing a plurality of database specifiers. Each of the database specifiers contains control information for the traversal of the primary and secondary databases. In addition, each of the nodes in the primary database and each of the entries in the secondary database is provided with control data structures that are programmable to control the traversal of the database.

摘要翻译： 本发明涉及包括耦合到查找数据库的地址识别引擎的地址识别装置。 查找数据库被设置为存储与网络地址有关的网络信息。 查找数据库包括主数据库和辅助数据库。 地址识别引擎接受需要网络信息的网络地址作为输入。 地址识别引擎使用网络地址作为主数据库的索引。 主数据库包括多路树节点结构（TRIE），其被布置为根据网络地址的预选段的顺序遍历节点，并且在段的固定序列中定位到辅助数据库中的条目的指针。 主数据库指针指向的辅助数据库中的条目包含与网络地址对应的网络信息。 地址识别引擎包括用于存储多个数据库说明符的表。 每个数据库说明符都包含用于遍历主数据库和辅助数据库的控制信息。 此外，主数据库中的每个节点和辅助数据库中的每个条目都具有可编程以控制数据库遍历的控制数据结构。

公开(公告)号：US5471632A

公开(公告)日：1995-11-28

申请号：US819468

申请日：1992-01-10

申请人： Vincent G. Gavin ,  Michael J. Seaman ,  Neal A. Crook ,  Bipin Mistry

发明人： Vincent G. Gavin ,  Michael J. Seaman ,  Neal A. Crook ,  Bipin Mistry

IPC分类号： G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4018

摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.

摘要翻译： 一种用于将处理器耦合到系统总线的数据传送装置。 数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。 字节或单词和长词之间。 数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。 处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

公开(公告)号：US5404474A

公开(公告)日：1995-04-04

申请号：US819393

申请日：1992-01-10

申请人： Neal A. Crook ,  Stewart F. Bryant ,  Michael J. Seaman ,  John M. Lenthall

发明人： Neal A. Crook ,  Stewart F. Bryant ,  Michael J. Seaman ,  John M. Lenthall

IPC分类号： G06F12/02 ,  G06F12/06

CPC分类号： G06F12/0223

摘要： A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.

摘要翻译： 一种用于对存储器系统中的位置进行混叠的地址的方法和装置。 混叠允许地址生成单元基于固定大小的地址空间访问可变大小的存储块，使得可以改变存储块的大小而不改变地址生成单元的地址生成软件。 本发明提供了一种地址混叠装置，其被布置成从地址生成单元接收地址。 地址混叠装置包括存储存储器块大小信息的寄存器。 存储器块大小信息由地址混叠器件读取并被解码以提供表示存储块大小的位信息。 地址混叠设备逻辑地将位信息与输入地址的适当对应位组合，以提供与存储块大小一致的别名地址。