公开(公告)号：US07551487B2

公开(公告)日：2009-06-23

申请号：US11716043

申请日：2007-03-09

申请人： Min-Gun Park ,  Sung-Jyu Jo

发明人： Min-Gun Park ,  Sung-Jyu Jo

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.

摘要翻译： 在非易失性存储器件中，第一验证结果指示存储器单元块是否已被成功编程，并且第二验证结果指示块中的远单元是否已被成功编程。 控制器响应于第一和第二验证结果定义在下一个程序循环期间施加的编程电压的电平和应用时间。

公开(公告)号：US20070136563A1

公开(公告)日：2007-06-14

申请号：US11424575

申请日：2006-06-16

申请人： Min-gun Park ,  Jin-yub Lee

发明人： Min-gun Park ,  Jin-yub Lee

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G11C16/34

摘要： Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

摘要翻译： 本发明的一些实施例提供了用于减少非易失性存储器件的编程时间的编程操作。 通过从主机接收要编程到存储器单元中的数据来编程非易失性半导体存储器件，将数据编程到存储器单元中，执行验证读取操作以确定数据是否被成功编程到存储器单元中，以及执行 Y扫描操作，同时执行验证读取操作以顺序地扫描和输出从耦合到存储器单元的位线读取的数据。

公开(公告)号：US20050141273A1

公开(公告)日：2005-06-30

申请号：US10957166

申请日：2004-09-30

申请人： Min-Gun Park ,  Jin-Yub Lee

发明人： Min-Gun Park ,  Jin-Yub Lee

IPC分类号： G06F12/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08

CPC分类号： G11C16/08

摘要： A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

摘要翻译： 一种能够以扇区为单位随机输入/输出数据的闪存系统。 闪存系统包括闪存（单元阵列），缓冲存储器，随机数据输入/输出电路和控制电路。 随机数据输入/输出电路以缓冲存储器的扇区为单位接收数据，或以扇区为单位将数据输出到缓冲存储器。 控制电路控制在缓冲存储器和随机数据输入/输出电路之间输入/输出数据的次序和次数。

公开(公告)号：US08495283B2

公开(公告)日：2013-07-23

申请号：US12947003

申请日：2010-11-16

申请人： Min Gun Park ,  Ki Tae Park

发明人： Min Gun Park ,  Ki Tae Park

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C7/04 ,  G11C13/0035 ,  G11C16/26 ,  G11C16/349

摘要： A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table.

摘要翻译： 非易失性存储器件包括存储器核心和用于控制非易失性存储器件中的存储器块的磨损水平的控制器。 控制器通过从存储单元的选定区域的电荷测量单元获取实际的磨损水平的数据来确定存储器块的磨损水平，并将所选区域的磨损水平存储在擦除计数表中。

公开(公告)号：US07636265B2

公开(公告)日：2009-12-22

申请号：US11264168

申请日：2005-11-02

申请人： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

发明人： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C16/3404

摘要： A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

摘要翻译： 提供了一种闪存器件，其包括适于将具有目标电压的编程电压提供给所选字线的高压发生器电路。 闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。 还提供了一种用于操作闪速存储器件的方法。

公开(公告)号：US07394700B2

公开(公告)日：2008-07-01

申请号：US11424575

申请日：2006-06-16

申请人： Min-gun Park ,  Jin-yub Lee

发明人： Min-gun Park ,  Jin-yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/34

摘要： Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

摘要翻译： 本发明的一些实施例提供了用于减少非易失性存储器件的编程时间的编程操作。 通过从主机接收要编程到存储器单元中的数据来编程非易失性半导体存储器件，将数据编程到存储器单元中，执行验证读取操作以确定数据是否被成功编程到存储器单元中，以及执行 Y扫描操作，同时执行验证读取操作以顺序地扫描和输出从耦合到存储器单元的位线读取的数据。

公开(公告)号：US07212426B2

公开(公告)日：2007-05-01

申请号：US10957166

申请日：2004-09-30

申请人： Min-Gun Park ,  Jin-Yub Lee

发明人： Min-Gun Park ,  Jin-Yub Lee

IPC分类号： G11C13/00

CPC分类号： G11C16/08

摘要： A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

摘要翻译： 一种能够以扇区为单位随机输入/输出数据的闪存系统。 闪存系统包括闪存（单元阵列），缓冲存储器，随机数据输入/输出电路和控制电路。 随机数据输入/输出电路以缓冲存储器的扇区为单位接收数据，或以扇区为单位将数据输出到缓冲存储器。 控制电路控制在缓冲存储器和随机数据输入/输出电路之间输入/输出数据的次序和次数。

公开(公告)号：US06930919B2

公开(公告)日：2005-08-16

申请号：US10788738

申请日：2004-02-26

申请人： Jin-Yub Lee ,  Dong-Kyu Youn ,  Min-Gun Park

发明人： Jin-Yub Lee ,  Dong-Kyu Youn ,  Min-Gun Park

IPC分类号： G11C16/00 ,  G11C11/34 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/34 ,  G11C16/0483

摘要： A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided. An example NAND-type flash memory device includes a status cell array which has a plurality of status cells and stores data indicating erase/program statuses of the memory blocks, a data generation circuit which generates data indicating a program status of a selected memory block in response to a data input command and generates data indicating an erase status of a selected memory block in response to a block erase setup command, a first signal generation circuit which generates a block status write enable signal and a clock signal in response to either one of an erase command and a program command, a selection circuit which selects at least one of the status cells of the status cell array in response to a block address of the selected memory block, a write circuit which receives data from the data generation circuit in response to the clock signal during a program or erase operation and writes the received data in the selected status cell, and a control circuit which operates in response to a block status write enable signal from the first signal generation circuit and controls the write circuit so as to the store the data inputted to the write circuit in a selected status cell when an erase/program operation for the selected memory block is carried out.

摘要翻译： 提供了包括具有多个存储块的存储单元阵列的NAND型闪速存储器件。 示例性的NAND型闪速存储器件包括具有多个状态单元并且存储指示存储块的擦除/程序状态的数据的状态单元阵列，产生指示所选存储块的程序状态的数据的数据生成电路 响应于数据输入命令并响应于块擦除设置命令产生指示所选存储器块的擦除状态的数据，产生块状态写使能信号的第一信号生成电路和响应于 擦除命令和程序命令;响应于所选存储器块的块地址选择状态单元阵列的状态单元中的至少一个的选择电路;响应于从数据生成电路接收数据的写入电路 在编程或擦除操作期间将时钟信号写入所选择的状态单元中，并将所接收的数据写入所选择的状态单元，以及控制电路， 对来自第一信号发生电路的块状态写入使能信号进行控制，并且当执行用于所选择的存储器块的擦除/编程操作时，控制写入电路以将输入到写入电路的数据存储在所选择的状态单元中 。

公开(公告)号：US20110235415A1

公开(公告)日：2011-09-29

申请号：US13070347

申请日：2011-03-23

申请人： Min Gun Park ,  Kit Tae Park

发明人： Min Gun Park ,  Kit Tae Park

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483

摘要： Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

摘要翻译： 提供了一种从非易失性存储装置读取数据的方法。 在该方法中，读取方法包括第一读取步骤，包括通过向第一存储单元施加第一组读取电压来读取非易失性存储器件的第一存储器单元。 读取方法还包括第二读取步骤，包括当确定第一读取步骤导致错误时，通过将第一组读取电压和第一组中的电压没有到第一存储器单元来读取第一存储器单元 并且不能用纠错校正。 通过使用从第一读取步骤得到的数据来执行第二读取步骤。

公开(公告)号：US20090175087A1

公开(公告)日：2009-07-09

申请号：US12247288

申请日：2008-10-08

申请人： Min-Gun PARK ,  Jin-Yub LEE

发明人： Min-Gun PARK ,  Jin-Yub LEE

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/0483

摘要： A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

摘要翻译： 提供了一种用于验证闪存设备的编程操作的方法。 闪速存储器件包括串联选择晶体管，多个存储单元和地选择晶体管串联连接的至少一个存储器串，并且相对于存储器串中的所选存储单元执行编程操作。 该方法包括将串联选择晶体管的阈值电压加到电源电压而获得的电压施加到连接到串选择晶体管的串选择线; 对连接到每个存储单元的字线和连接到地选择晶体管的接地选择线施加接地电压; 将连接到存储器串的位线预充电到电源电压; 以及确定所选存储单元的编程操作是否完成。