公开(公告)号：US20050141273A1

公开(公告)日：2005-06-30

申请号：US10957166

申请日：2004-09-30

申请人： Min-Gun Park ,  Jin-Yub Lee

发明人： Min-Gun Park ,  Jin-Yub Lee

IPC分类号： G06F12/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08

CPC分类号： G11C16/08

摘要： A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

摘要翻译： 一种能够以扇区为单位随机输入/输出数据的闪存系统。 闪存系统包括闪存（单元阵列），缓冲存储器，随机数据输入/输出电路和控制电路。 随机数据输入/输出电路以缓冲存储器的扇区为单位接收数据，或以扇区为单位将数据输出到缓冲存储器。 控制电路控制在缓冲存储器和随机数据输入/输出电路之间输入/输出数据的次序和次数。

公开(公告)号：US07212426B2

公开(公告)日：2007-05-01

申请号：US10957166

申请日：2004-09-30

申请人： Min-Gun Park ,  Jin-Yub Lee

发明人： Min-Gun Park ,  Jin-Yub Lee

IPC分类号： G11C13/00

CPC分类号： G11C16/08

摘要： A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

摘要翻译： 一种能够以扇区为单位随机输入/输出数据的闪存系统。 闪存系统包括闪存（单元阵列），缓冲存储器，随机数据输入/输出电路和控制电路。 随机数据输入/输出电路以缓冲存储器的扇区为单位接收数据，或以扇区为单位将数据输出到缓冲存储器。 控制电路控制在缓冲存储器和随机数据输入/输出电路之间输入/输出数据的次序和次数。

公开(公告)号：US06930919B2

公开(公告)日：2005-08-16

申请号：US10788738

申请日：2004-02-26

申请人： Jin-Yub Lee ,  Dong-Kyu Youn ,  Min-Gun Park

发明人： Jin-Yub Lee ,  Dong-Kyu Youn ,  Min-Gun Park

IPC分类号： G11C16/00 ,  G11C11/34 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/34 ,  G11C16/0483

摘要： A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided. An example NAND-type flash memory device includes a status cell array which has a plurality of status cells and stores data indicating erase/program statuses of the memory blocks, a data generation circuit which generates data indicating a program status of a selected memory block in response to a data input command and generates data indicating an erase status of a selected memory block in response to a block erase setup command, a first signal generation circuit which generates a block status write enable signal and a clock signal in response to either one of an erase command and a program command, a selection circuit which selects at least one of the status cells of the status cell array in response to a block address of the selected memory block, a write circuit which receives data from the data generation circuit in response to the clock signal during a program or erase operation and writes the received data in the selected status cell, and a control circuit which operates in response to a block status write enable signal from the first signal generation circuit and controls the write circuit so as to the store the data inputted to the write circuit in a selected status cell when an erase/program operation for the selected memory block is carried out.

摘要翻译： 提供了包括具有多个存储块的存储单元阵列的NAND型闪速存储器件。 示例性的NAND型闪速存储器件包括具有多个状态单元并且存储指示存储块的擦除/程序状态的数据的状态单元阵列，产生指示所选存储块的程序状态的数据的数据生成电路 响应于数据输入命令并响应于块擦除设置命令产生指示所选存储器块的擦除状态的数据，产生块状态写使能信号的第一信号生成电路和响应于 擦除命令和程序命令;响应于所选存储器块的块地址选择状态单元阵列的状态单元中的至少一个的选择电路;响应于从数据生成电路接收数据的写入电路 在编程或擦除操作期间将时钟信号写入所选择的状态单元中，并将所接收的数据写入所选择的状态单元，以及控制电路， 对来自第一信号发生电路的块状态写入使能信号进行控制，并且当执行用于所选择的存储器块的擦除/编程操作时，控制写入电路以将输入到写入电路的数据存储在所选择的状态单元中 。

公开(公告)号：US07907454B2

公开(公告)日：2011-03-15

申请号：US12247288

申请日：2008-10-08

申请人： Min-Gun Park ,  Jin-yub Lee

发明人： Min-Gun Park ,  Jin-yub Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/0483

摘要： A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

摘要翻译： 提供了一种用于验证闪存设备的编程操作的方法。 闪速存储器件包括串联选择晶体管，多个存储单元和地选择晶体管串联连接的至少一个存储器串，并且相对于存储器串中的所选存储单元执行编程操作。 该方法包括将串联选择晶体管的阈值电压加到电源电压而获得的电压施加到连接到串选择晶体管的串选择线; 对连接到每个存储单元的字线和连接到地选择晶体管的接地选择线施加接地电压; 将连接到存储器串的位线预充电到电源电压; 以及确定所选存储单元的编程操作是否完成。

公开(公告)号：US07974128B2

公开(公告)日：2011-07-05

申请号：US12620758

申请日：2009-11-18

申请人： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

发明人： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3404

摘要： A flash memory device including a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

摘要翻译： 提供了一种包括适于向所选字线提供具有目标电压的编程电压的高压发生器电路的闪速存储器件。 闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。 还提供了一种用于操作闪速存储器件的方法。

公开(公告)号：US07551487B2

公开(公告)日：2009-06-23

申请号：US11716043

申请日：2007-03-09

申请人： Min-Gun Park ,  Sung-Jyu Jo

发明人： Min-Gun Park ,  Sung-Jyu Jo

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.

摘要翻译： 在非易失性存储器件中，第一验证结果指示存储器单元块是否已被成功编程，并且第二验证结果指示块中的远单元是否已被成功编程。 控制器响应于第一和第二验证结果定义在下一个程序循环期间施加的编程电压的电平和应用时间。

公开(公告)号：US20060227607A1

公开(公告)日：2006-10-12

申请号：US11298186

申请日：2005-12-08

申请人： Min-Gun Park ,  Seong-Kue Jo

发明人： Min-Gun Park ,  Seong-Kue Jo

IPC分类号： G11C16/04

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.

摘要翻译： 非易失性存储器件执行多页复印操作，其中在从一个或多个垫读出的多个复印数据被顺序地存储在多个缓冲器中之后，所存储的数据被同时编程到不同的垫。 拷贝数据可以被读出，而不限于垫子的位置和要从各个垫子读出的拷贝数据的数量。 读出的拷贝数据同时被编程到多个垫。

公开(公告)号：US20060136649A1

公开(公告)日：2006-06-22

申请号：US11224662

申请日：2005-09-12

申请人： Min-Gun Park ,  Jin-Wook Lee

发明人： Min-Gun Park ,  Jin-Wook Lee

IPC分类号： G06F13/40

CPC分类号： G06F13/1673 ,  G06F13/1678 ,  G06F13/1689

摘要： In a flash memory data storage apparatus, a multistage flash input buffer unit is embedded in which data bus width is gradually extended and the period of a control clock is gradually made longer. In one example, the flash memory data storage apparatus renders its embedded flash memory to be accessed with 128-bit data in parallel in a period of 80 ns, while communicating with an external system for 16-bit data in parallel during a period of 20 ns. The flash memory data storage apparatus improves a data rate between the flash memory and a buffer memory, resulting in remarkable advancement of the data rate between the flash memory and an external system.

摘要翻译： 在闪速存储器数据存储装置中，埋入多级闪存输入缓冲器单元，其中数据总线宽度逐渐延长，控制时钟的周期逐渐变长。 在一个示例中，闪速存储器数据存储装置使其嵌入式闪速存储器在80ns的时段内并行地与128位数据并行访问，同时在20个周期内并行地与外部系统进行16位数据的并行通信 ns。 闪速存储器数据存储装置提高了闪速存储器和缓冲存储器之间的数据速率，导致闪速存储器和外部系统之间的数据速率显着提高。

公开(公告)号：US07636265B2

公开(公告)日：2009-12-22

申请号：US11264168

申请日：2005-11-02

申请人： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

发明人： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C16/3404

摘要： A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

摘要翻译： 提供了一种闪存器件，其包括适于将具有目标电压的编程电压提供给所选字线的高压发生器电路。 闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。 还提供了一种用于操作闪速存储器件的方法。

公开(公告)号：US07467251B2

公开(公告)日：2008-12-16

申请号：US11224662

申请日：2005-09-12

申请人： Min-Gun Park ,  Jin-Wook Lee

发明人： Min-Gun Park ,  Jin-Wook Lee

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/14

CPC分类号： G06F13/1673 ,  G06F13/1678 ,  G06F13/1689

摘要： A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i−l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i−1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.

摘要翻译： 闪存数据存储装置包括闪存和闪存接口。 闪存通过闪存总线组收发数据。 闪存接口包括第一至第n个闪存输入缓冲器，其响应于第一至第n个传输时钟控制信号将数据分阶段地传送到主机总线组。 至少第一个闪存输入缓冲器通过第i个输入缓冲区总线组提供数据。 第i个输入缓冲器总线组中的每一个的总线宽度比第（i-1）个输入缓冲器总线组中的每一个的总线宽度宽。 第i个传送时钟控制信号的周期比第（i-1）个传输时钟控制信号的周期长。 通过将闪存总线组的总线宽度除以每个第i个输入缓冲器总线组的总线宽度来划分闪存总线组的总线宽度来获得Ni。