公开(公告)号：US20110194353A1

公开(公告)日：2011-08-11

申请号：US13022688

申请日：2011-02-08

Applicant: Sang-Won Hwang ,  Chan-Ho Kim

Inventor： Sang-Won Hwang ,  Chan-Ho Kim

IPC: G11C16/10

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/3454

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract translation: 提供了一种用于非易失性存储器件的存储器单元的编程方法。 该方法包括基于编程电压，第一验证电压和第二验证电压来执行增量步进脉冲程序（ISPP）操作，并且基于存储器的第一通过失败结果来改变编程电压的增量值 基于第一验证电压产生第一通过失败结果。 基于存储单元的第二通过失败结果完成ISPP操作，基于第二验证电压生成第二通过失败结果。

公开(公告)号：US07911841B2

公开(公告)日：2011-03-22

申请号：US11606290

申请日：2006-11-30

Applicant: Sang-Won Hwang

Inventor： Sang-Won Hwang

IPC: G01R31/28 ,  G11C7/00

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C29/804 ,  G11C2211/5641

Abstract: A non-volatile memory may include a flag cell array, wherein each flag cell is arranged in the memory cell array interspersed among the plurality of memory cells. The flag cell array may include a plurality of flag cells indicating whether a corresponding row is MSB programmed. The non-volatile memory device performs an algorithm to read out data stored in the memory cell based on whether the memory cells of a row are MSB programmed. When determining whether the corresponding row is MSB programmed, a flag cell that is not normally operated may be replaced by a redundancy flag cell or data of the flag cell that is not normally operated may be excluded. Thus, the reliability in reading out of data and the production yield of the non-volatile memory may be improved.

Abstract translation: 非易失性存储器可以包括标志单元阵列，其中每个标志单元布置在散布在多个存储单元之间的存储单元阵列中。 标志单元阵列可以包括指示相应行是否被编程为MSB的多个标志单元。 非易失性存储器件基于一行的存储器单元是否被编程为MSB，执行读出存储在存储器单元中的数据的算法。 当确定对应的行是否被编程为MSB时，不正常操作的标志单元可以由冗余标志单元代替，或者可以排除不正常操作的标志单元的数据。 因此，可以提高读取数据的可靠性和非易失性存储器的生产率。

公开(公告)号：US07710773B2

公开(公告)日：2010-05-04

申请号：US12350588

申请日：2009-01-08

Applicant: Sang Won Hwang

Inventor： Sang Won Hwang

IPC: G11C16/04 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5641

Abstract: A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of memory cells and the additional block of virtual memory cells may be read independently to provide a total of three blocks of read data.

Abstract translation: 非易失性存储器阵列包括其中的三态存储器单元的第一和第二块。 这些第一和第二块被配置为分别作为物理存储器单元的第一和第二块单独地操作，并且共同地作为虚拟存储器单元的附加块进行操作。 存储器单元的第一和第二块和虚拟存储器单元的附加块可以独立地读取以提供总共三个读取数据块。

公开(公告)号：US07660159B2

公开(公告)日：2010-02-09

申请号：US10998987

申请日：2004-11-30

Applicant: Sang-won Hwang ,  Jin-Yub Lee ,  Bum-Soo Kim ,  Kwang-Yoon Lee ,  Chan-Ik Park

Inventor： Sang-won Hwang ,  Jin-Yub Lee ,  Bum-Soo Kim ,  Kwang-Yoon Lee ,  Chan-Ik Park

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3454

Abstract: Methods and devices for programming control information perform a lower-speed programming of a given cell type in a first area of memory array, confirm a result of the lower-speed programming of the given cell type in the first area of memory array, and perform a higher-speed programming of the given cell type in a second area of memory array after confirming the result of the lower-speed programming. An initial programming voltage of the higher-speed programming may be different from that of the lower-speed programming. The first programming may be a lower-speed operation, such as the writing of data, and the second programming may be a higher-speed operation, such as the writing of control information.

Abstract translation: 用于编程控制信息的方法和装置在存储器阵列的第一区域中执行给定小区类型的较低速度编程，确认存储器阵列的第一区域中给定小区类型的较低速度编程的结果，并执行 在确认低速编程的结果之后，在存储器阵列的第二区域中对给定单元类型的更高速度编程。 较高速度编程的初始编程电压可能与低速编程的编程电压不同。 第一编程可以是诸如写入数据的低速操作，并且第二编程可以是诸如写入控制信息的更高速的操作。

公开(公告)号：US07480187B2

公开(公告)日：2009-01-20

申请号：US11356417

申请日：2006-02-17

Applicant: Sang-Won Hwang

Inventor： Sang-Won Hwang

IPC: G11C11/30

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/14

Abstract: A NAND flash memory device includes an array of NAND flash memory cells; a plurality of word lines connected to the NAND flash memory cells; and a plurality of bit lines connected to the NAND flash memory cells. Each bit line includes a first bit line portion, a second bit line portion, and a switching device extending between the first and second bit line portions to selectively connect the first and second bit line portions together. At least a first NAND flash memory cell is connected to the first bit line portion, and at least a second NAND flash memory cell is connected to the second bit line portion. By including primary and secondary page buffers, two pages of memory cells connected to a same group of bit lines can be programmed in a single programming operation, to achieve “double-speed” programming.

Abstract translation: NAND闪速存储器件包括NAND闪存单元的阵列; 连接到NAND闪存单元的多个字线; 以及连接到NAND闪存单元的多个位线。 每个位线包括第一位线部分，第二位线部分和在第一和第二位线部分之间延伸的选择性地将第一和第二位线部分连接在一起的开关器件。 至少第一NAND闪存单元连接到第一位线部分，并且至少第二NAND闪存单元连接到第二位线部分。 通过包括主页缓冲器和次页面缓冲器，可以在单个编程操作中编程连接到同一组位线的两页存储单元，以实现“双速”编程。

公开(公告)号：US20080266951A1

公开(公告)日：2008-10-30

申请号：US12106472

申请日：2008-04-21

Applicant: Sang-Won HWANG

Inventor： Sang-Won HWANG

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device, related memory system, and program method for the non-volatile memory device are disclosed. In the method, memory cells in a memory cell array are accessed through a plurality of word lines by applying a program voltage to a selected word line, wherein the selected word line is not adjacent to an outmost word line, applying a first reduced pass voltage to word lines adjacent to the selected word line, and applying a second reduced pass voltage to the outermost word lines.

Abstract translation: 公开了一种用于非易失性存储器件的非易失性存储器件，相关存储器系统和程序方法。 在该方法中，通过对所选字线施加编程电压，通过多个字线来访问存储单元阵列中的存储单元，其中所选字线不与最外边的字线相邻，施加第一降压电压 到与选定字线相邻的字线，以及向最外面的字线施加第二降压电压。

公开(公告)号：US07388778B2

公开(公告)日：2008-06-17

申请号：US11358648

申请日：2006-02-21

Applicant: Sang Won Hwang

Inventor： Sang Won Hwang

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5641

Abstract: A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of memory cells and the additional block of virtual memory cells may be read independently to provide a total of three blocks of read data.

Abstract translation: 非易失性存储器阵列包括其中的三态存储器单元的第一和第二块。 这些第一和第二块被配置为分别作为物理存储器单元的第一和第二块单独地操作，并且共同地作为虚拟存储器单元的附加块进行操作。 存储器单元的第一和第二块和虚拟存储器单元的附加块可以独立地读取以提供总共三个读取数据块。

公开(公告)号：US07372754B2

公开(公告)日：2008-05-13

申请号：US11354917

申请日：2006-02-16

Applicant: Sang-Won Hwang ,  Jin-Wook Lee

Inventor： Sang-Won Hwang ,  Jin-Wook Lee

IPC: G11C7/00

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

Abstract: A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.

Abstract translation: 非易失性存储器件包括非易失性存储单元阵列，包括连接到多个字线的多个非易失性存储器单元，字线电压发生器，被配置为产生第一和第二电压脉冲序列。 该装置选择性地将第一和第二电压脉冲序列中的一个提供给选定的字线之一，以编程连接到所选字线的非易失存储器单元。 电压脉冲的第一序列的至少一个电压脉冲的斜率大于第二电压脉冲序列的至少一个电压脉冲的斜率。 通常，第一个序列应用于远离字符串选择行（SSL）的字线，第二个序列应用于接近SSL的字线。

公开(公告)号：US07315480B2

公开(公告)日：2008-01-01

申请号：US11444353

申请日：2006-06-01

Applicant: You-Sang Lee ,  Sang-Won Hwang

Inventor： You-Sang Lee ,  Sang-Won Hwang

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C29/846

Abstract: A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up; a sense amplifier block for sensing and amplifying data bits from ROM cells of the respective rows selected sequentially according to the control of the ROM controller; a latch block for receiving data bits sensed by the sense amplifier block through a switch circuit and latching the input data bits as a defective address; and a comparator block for detecting whether an address input in a normal operation matches one of the defective addresses stored in the latch block. As the rows are sequentially selected, the defective addresses of the ROM cell array are transferred to the latch block through the sense amplifier block by means of serial transfer.

Abstract translation: 在非易失性存储装置中使用的冗余选择器电路包括ROM阵列，其中存储有不良地址的ROM单元阵列，包括以行和列为矩阵排列的多个ROM单元; ROM控制器，用于在加电时依次选择ROM单元阵列的行; 读出放大器模块，用于根据ROM控制器的控制来依次选择依次选择的各个ROM单元的数据位; 锁存块，用于通过开关电路接收由读出放大器块检测的数据位，并将输入数据位锁存为缺陷地址; 以及用于检测在正常操作中输入的地址是否匹配存储在锁存块中的缺陷地址中的一个的比较器块。 当依次选择行时，ROM单元阵列的缺陷地址通过串行传输通过读出放大器块传送到锁存块。

公开(公告)号：US20070234183A1

公开(公告)日：2007-10-04

申请号：US11605977

申请日：2006-11-30

Applicant: Sang-Won Hwang ,  Jong-Soo Lee

Inventor： Sang-Won Hwang ,  Jong-Soo Lee

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/00 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data, an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information, and a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.

Abstract translation: 公开了非易失性存储器件，存储器系统和读取方法。 存储器件包括存储单元阵列，其包括多个存储器块，每个存储块具有适于存储N位的多个存储器单元，其中N是大于1的整数，被配置为执行适于从 存储单元阵列和输出读取数据，错误校正电路，被配置为检测和校正存储在存储块K中的读取数据中的错误并产生相应的错误信息;以及控制电路，被配置为减少存储在多个存储单元阵列中的位数 用于存储块K从N到J的存储器单元，其中J是小于N但大于零的整数，其响应于错误信息。