公开(公告)号：US20110142325A1

公开(公告)日：2011-06-16

申请号：US12968725

申请日：2010-12-15

申请人： Yoonna OH ,  Jae-Pil Shin ,  Jin Choi ,  Moon-Hyun Yoo ,  Jong-Bae Lee

发明人： Yoonna OH ,  Jae-Pil Shin ,  Jin Choi ,  Moon-Hyun Yoo ,  Jong-Bae Lee

IPC分类号： G06K9/00

CPC分类号： G06T7/0006 ,  G03F1/84 ,  G06T2207/10061 ,  G06T2207/20068 ,  G06T2207/30148

摘要： In a method of inspecting a mask, an image of a pattern on the mask may be obtained. A histogram of the image by grey levels may be obtained. The histogram may be compared with information of the pattern to detect a defect of the mask. Thus, reliability of defect detection in the mask may be remarkably improved.

摘要翻译： 在检查掩模的方法中，可以获得掩模上的图案的图像。 可以获得灰度级的图像的直方图。 可以将直方图与图案的信息进行比较以检测掩模的缺陷。 因此，掩模中的缺陷检测的可靠性可以显着提高。

公开(公告)号：US07617065B2

公开(公告)日：2009-11-10

申请号：US11698690

申请日：2007-01-26

申请人： Dae-Wook Kim ,  Sang-Hoon Lee ,  Ji-Seong Doh ,  Moon-Hyun Yoo ,  Jong-Bae Lee

发明人： Dae-Wook Kim ,  Sang-Hoon Lee ,  Ji-Seong Doh ,  Moon-Hyun Yoo ,  Jong-Bae Lee

IPC分类号： G06F17/00

CPC分类号： G06F17/5009 ,  G01R31/31711 ,  G01R31/318314 ,  G06F2217/10 ,  G06F2217/78

摘要： A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by measuring electrical characteristics of the plurality of transistors included in the plurality of chips, extracting an inter-chip distribution characteristic and an intra-chip distribution characteristic of the electrical characteristics by analyzing the electrical characteristic data, generating random number data satisfying the extracted inter-chip and intra-chip distribution characteristics, and performing a simulation for extracting statistical distribution characteristic data of the physical parameters of the chips, based on the random number data.

摘要翻译： 一种用于估计半导体器件的物理参数的统计分布特性的方法包括制造多个半导体器件芯片，每个半导体器件芯片具有多个晶体管，通过测量包括在多个芯片中的多个晶体管的电特性来制备电特性数据， 通过分析电特性数据，产生满足提取的芯片间和片内分布特性的随机数数据，提取电特性的片间分布特性和芯片内分布特性，并执行用于提取统计分布的模拟 基于随机数数据的芯片的物理参数的特征数据。

公开(公告)号：US07361435B2

公开(公告)日：2008-04-22

申请号：US11289204

申请日：2005-11-28

申请人： Chul-Hong Park ,  Moon-Hyun Yoo ,  Yoo-Hyon Kim ,  Dong-Hyun Kim ,  Soo-Han Choi

发明人： Chul-Hong Park ,  Moon-Hyun Yoo ,  Yoo-Hyon Kim ,  Dong-Hyun Kim ,  Soo-Han Choi

IPC分类号： G03F1/00 ,  G03F1/14 ,  G06F17/50

CPC分类号： G03F1/30 ,  G03F1/32 ,  G03F1/70 ,  G03F7/70466

摘要： A method of creating a layout of a set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

摘要翻译： 提供了一种创建包括交替相移掩模（APSM）和半色调相移修剪蒙版（HPSTM）的掩模组的布局的方法。 APSM包括第一和第二相移区域和第一不透明图案。 第一和第二相移区域彼此相邻设置并且具有不同的相位以产生破坏性干扰。 此外，第一和第二相移区域限定了接入互连线。 第一不透明图案形成在透明基板上以限定第一和第二相移区域。 HPSTM在透明基板上包括第二不透明图案和半色调图案。 第二个不透明图案防止访问互连线被擦除。 半色调图案定义了连接到接入互连线的通过互连线。

公开(公告)号：US20080076047A1

公开(公告)日：2008-03-27

申请号：US11589026

申请日：2006-10-27

申请人： Yong-jin Chun ,  Doo-youl Lee ,  Moon-hyun Yoo ,  Suk-joo Lee

发明人： Yong-jin Chun ,  Doo-youl Lee ,  Moon-hyun Yoo ,  Suk-joo Lee

IPC分类号： G03C5/00

CPC分类号： G03F1/36

摘要： A method of forming an image contour for predicting a pattern image formed on a wafer from a layout of a semiconductor device includes: forming a basic layout for a semiconductor device; performing an optical proximity effect correction (OPC) on the basic layout to form an OPC layout; defining nonlinear regions and linear regions of the basic layout; emulating the nonlinear regions of the basic layout using the OPC layout to form an image contour of the nonlinear regions; determining the linear regions of the basic layout as an image contour of the linear regions; and combining the image contour of the nonlinear regions and image contour of the linear regions to form an image contour of the entire semiconductor device.

摘要翻译： 根据半导体器件的布局形成用于预测在晶片上形成的图案图像的图像轮廓的方法包括：形成用于半导体器件的基本布局; 在基本布局上执行光学邻近效应校正（OPC）以形成OPC布局; 定义基本布局的非线性区域和线性区域; 使用OPC布局模拟基本布局的非线性区域，以形成非线性区域的图像轮廓; 将所述基本布局的线性区域确定为所述线性区域的图像轮廓; 并且组合非线性区域的图像轮廓和线性区域的图像轮廓以形成整个半导体器件的图像轮廓。

公开(公告)号：US20070192077A1

公开(公告)日：2007-08-16

申请号：US11698690

申请日：2007-01-26

申请人： Dae-Wook Kim ,  Sang-Hoon Lee ,  Ji-Seong Doh ,  Moon-Hyun Yoo ,  Jong-Bae Lee

发明人： Dae-Wook Kim ,  Sang-Hoon Lee ,  Ji-Seong Doh ,  Moon-Hyun Yoo ,  Jong-Bae Lee

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/5009 ,  G01R31/31711 ,  G01R31/318314 ,  G06F2217/10 ,  G06F2217/78

摘要： A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by measuring electrical characteristics of the plurality of transistors included in the plurality of chips, extracting an inter-chip distribution characteristic and an intra-chip distribution characteristic of the electrical characteristics by analyzing the electrical characteristic data, generating random number data satisfying the extracted inter-chip and intra-chip distribution characteristics, and performing a simulation for extracting statistical distribution characteristic data of the physical parameters of the chips, based on the random number data.

摘要翻译： 一种用于估计半导体器件的物理参数的统计分布特性的方法包括制造多个半导体器件芯片，每个半导体器件芯片具有多个晶体管，通过测量包括在多个芯片中的多个晶体管的电特性来制备电特性数据， 通过分析电特性数据，产生满足提取的芯片间和片内分布特性的随机数数据，提取电特性的片间分布特性和芯片内分布特性，并执行用于提取统计分布的模拟 基于随机数数据的芯片的物理参数的特征数据。

公开(公告)号：US20070174802A1

公开(公告)日：2007-07-26

申请号：US11625569

申请日：2007-01-22

申请人： Jae-Pil SHIN ,  Moon-Hyun Yoo ,  Jong-Bae Lee ,  Jin-Sook Choi ,  Sung Gyu Park

发明人： Jae-Pil SHIN ,  Moon-Hyun Yoo ,  Jong-Bae Lee ,  Jin-Sook Choi ,  Sung Gyu Park

IPC分类号： G06F17/50

CPC分类号： G03F1/80 ,  G03F1/36

摘要： A method of adjusting pattern density includes determining a reference pattern density, defining dummy generation fields and designed patterns, forming basic dummy patterns on the dummy generation fields, evaluating a total pattern density from a sum of a density of the designed patterns and a density of the basic dummy patterns, adjusting a size of the basic dummy patterns so that the total pattern density reaches the reference pattern density, and combining data of the adjusted dummy patterns with data of the designed patterns.

摘要翻译： 调整图案密度的方法包括确定参考图案密度，定义虚拟生成区域和设计图案，在虚拟生成区域上形成基本虚拟图案，从设计图案的密度和密度之和评估总图案密度 基本虚拟图案，调整基本虚拟图案的尺寸，使得总图案密度达到参考图案密度，以及将调整的图案数据与设计图案的数据组合。

公开(公告)号：US07159202B2

公开(公告)日：2007-01-02

申请号：US10629154

申请日：2003-07-29

申请人： Jong-bae Lee ,  Moon-hyun Yoo ,  Kyo-sun Kim ,  Jeong-min Choi

发明人： Jong-bae Lee ,  Moon-hyun Yoo ,  Kyo-sun Kim ,  Jeong-min Choi

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068

摘要： Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein. These embodiments may also be configured to generate a layout schematic from the first schematic of the integrated circuit and generate parasitic resistances and capacitances of the post-layout interconnects that extend between a plurality of cells in the layout schematic. Operations are then performed to generate parasitic resistances and capacitances of interconnects internal to at least one cell in the layout schematic.

摘要翻译： 用于产生集成电路网表的操作包括生成其中具有多个单元的集成电路的第一原理图，并且生成限定集成电路的多个单元之间的预布置电互连的第二示意图，并且近似寄生电阻和寄生电容 的预布局互连。 然后，第一和第二原理图分别在第一和第二示意图中的对应的第一和第二端口组合。 操作还包括通过产生限定集成电路的多个单元之间的布局后互连的电路原理图来生成集成电路网表，并且近似寄生电阻和后布局互连的寄生电容。 然后将该电路示意图与其中的相应的第一和第二端口与第一示意图组合。 这些实施例还可以被配置为从集成电路的第一原理图生成布局示意图，并且生成在布局原理图中在多个单元之间延伸的布局后互连的寄生电阻和电容。 然后执行操作以在布局原理图中产生至少一个单元的内部的互连的寄生电阻和电容。

公开(公告)号：US20060190862A1

公开(公告)日：2006-08-24

申请号：US11336744

申请日：2006-01-19

申请人： Seuk-Whan Lee ,  Moon-Hyun Yoo ,  Joon-Ho Choi

发明人： Seuk-Whan Lee ,  Moon-Hyun Yoo ,  Joon-Ho Choi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for simulating an integrated circuit includes performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement, identifying a weak signal node based on the simulation result, and performing a size tuning operation on the weak signal node of the integrated circuit.

公开(公告)号：US08045787B2

公开(公告)日：2011-10-25

申请号：US12006877

申请日：2008-01-07

申请人： Soo-han Choi ,  Yong-jin Chun ,  Moon-hyun Yoo ,  Joon-ho Choi ,  Ji-suk Hong

发明人： Soo-han Choi ,  Yong-jin Chun ,  Moon-hyun Yoo ,  Joon-ho Choi ,  Ji-suk Hong

IPC分类号： G06K9/00

CPC分类号： G03F7/70433 ,  G03F1/36 ,  G03F7/705 ,  G03F7/70666

摘要： Provided are a system for analyzing a mask topography, which can reduce calculation time and increase calculation accuracy in consideration of a mask topography effect, and a method of forming an image using the system. The system and method simultaneously obtains a first electric field using a Kirchhoff method without considering a pitch formed on a mask and obtains a second electric field using an electromagnetic field analysis method considering the pitch, and then determines a third electric field on a pupil surface of a projection lens by combining the first electric field and the second electric field of forming an image, so as to calculate the image of an optical lithography system which includes an illumination system and a projection optical system and to which the projection lens belongs.

摘要翻译： 提供了一种用于分析掩模形貌的系统，其可以减少考虑到掩模形貌效应的计算时间和增加计算精度，以及使用该系统形成图像的方法。 该系统和方法同时使用基尔霍夫方法获得第一电场，而不考虑在掩模上形成的间距，并且使用考虑到间距的电磁场分析方法获得第二电场，然后确定瞳孔表面上的第三电场 通过组合形成图像的第一电场和第二电场的投影透镜，以计算包括照明系统和投影光学系统并且投影透镜所属的光学系统的图像。

公开(公告)号：US07913207B2

公开(公告)日：2011-03-22

申请号：US11649628

申请日：2007-01-04

申请人： Sang-ho Park ,  Jong-bae Lee ,  Moon-hyun Yoo ,  Ho Shim ,  Jin-won Kim

发明人： Sang-ho Park ,  Jong-bae Lee ,  Moon-hyun Yoo ,  Ho Shim ,  Jin-won Kim

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

CPC分类号： G06F17/5031 ,  G06F17/5022

摘要： A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

摘要翻译： 一种用于验证逻辑电路的方法和装置，其能够更快的操作，被应用于逻辑门级或晶体管级电路设计，以及验证信号的定时和模拟信号特性。 逻辑电路验证方法包括波形文件生成阶段和逻辑电路验证阶段。 波形文件生成阶段使用逻辑电路的设计源文件生成包括逻辑电路的所有节点的波形的波形文件。 逻辑电路的验证阶段使用设计参考文件验证逻辑电路，该设计参考文件包括逻辑电路的所有节点和波形文件的理想操作。