公开(公告)号：US08642435B2

公开(公告)日：2014-02-04

申请号：US13349969

申请日：2012-01-13

申请人： Che-Cheng Chang ,  Po-Chi Wu ,  Chang-Yin Chen ,  Zhe-Hao Zhang ,  Yi-Chen Huang

发明人： Che-Cheng Chang ,  Po-Chi Wu ,  Chang-Yin Chen ,  Zhe-Hao Zhang ,  Yi-Chen Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

摘要翻译： 一种方法包括在半导体衬底上形成栅极堆叠，其中栅极堆叠包括栅极电介质和位于栅极电介质上的栅电极。 与栅叠层相邻的半导体衬底的一部分被凹入以形成凹部。 半导体区域在凹槽中外延生长。 半导体区域注入p型杂质或n型杂质。 在半导体区域进行干法处理。

公开(公告)号：US08927358B2

公开(公告)日：2015-01-06

申请号：US13286605

申请日：2011-11-01

申请人： Po-Chi Wu ,  Ryan Chia-Jen Chen

发明人： Po-Chi Wu ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/441 ,  H01L21/3205 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L21/02186 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

摘要翻译： 具有通过接触金属层的蚀刻溶液的组成确定的可选择阈值电压的金属氧化物半导体（MOS）器件。 MOS器件可以是p型或n型MOS，并且对于两种类型的MOS器件都可以选择阈值电压。 蚀刻溶液是含氧溶液或含氟化物溶液。 通过调节惰性气体进入蚀刻室的流量来控制阈值电压，以控制氧气或三氟化氮的浓度。

公开(公告)号：US20130181262A1

公开(公告)日：2013-07-18

申请号：US13349969

申请日：2012-01-13

申请人： Che-Cheng Chang ,  Po-Chi Wu ,  Chang-Yin Chen ,  Zhe-Hao Zhang ,  Yi-Chen Huang

发明人： Che-Cheng Chang ,  Po-Chi Wu ,  Chang-Yin Chen ,  Zhe-Hao Zhang ,  Yi-Chen Huang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

摘要翻译： 一种方法包括在半导体衬底上形成栅极堆叠，其中栅极堆叠包括栅极电介质和位于栅极电介质上的栅电极。 与栅叠层相邻的半导体衬底的一部分被凹入以形成凹部。 半导体区域在凹槽中外延生长。 半导体区域注入p型杂质或n型杂质。 在半导体区域进行干法处理。

公开(公告)号：US20130146993A1

公开(公告)日：2013-06-13

申请号：US13314462

申请日：2011-12-08

申请人： Che-Cheng CHANG ,  Po-chi WU ,  Buh-Kuan FANG ,  Jr-Jung LIN ,  Ryan Chia-Jen CHEN

发明人： Che-Cheng CHANG ,  Po-chi WU ,  Buh-Kuan FANG ,  Jr-Jung LIN ,  Ryan Chia-Jen CHEN

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/02071 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7843

摘要： The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

摘要翻译： 本申请公开了一种形成半导体结构的方法。 在至少一个实施例中，该方法包括在衬底上形成多晶硅层。 在多晶硅层上形成掩模层。 图案化掩模层以形成图案化掩模层。 通过使用图案化掩模层作为掩模蚀刻多晶硅层来形成多晶硅结构。 多晶硅结构具有上表面和下表面，并且多晶硅层的蚀刻被布置成使得多晶硅结构的上表面的宽度大于多晶硅结构的下表面的宽度。

公开(公告)号：US08574989B2

公开(公告)日：2013-11-05

申请号：US13314462

申请日：2011-12-08

申请人： Che-Cheng Chang ,  Po-Chi Wu ,  Buh-Kuan Fang ,  Jr-Jung Lin ,  Ryan Chia-Jen Chen

发明人： Che-Cheng Chang ,  Po-Chi Wu ,  Buh-Kuan Fang ,  Jr-Jung Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/02071 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7843

摘要： The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

摘要翻译： 本申请公开了一种形成半导体结构的方法。 在至少一个实施例中，该方法包括在衬底上形成多晶硅层。 在多晶硅层上形成掩模层。 图案化掩模层以形成图案化掩模层。 通过使用图案化掩模层作为掩模蚀刻多晶硅层来形成多晶硅结构。 多晶硅结构具有上表面和下表面，并且多晶硅层的蚀刻被布置成使得多晶硅结构的上表面的宽度大于多晶硅结构的下表面的宽度。

公开(公告)号：US08530317B1

公开(公告)日：2013-09-10

申请号：US13587123

申请日：2012-08-16

申请人： Po-Chi Wu ,  Buh-Kuan Fang

发明人： Po-Chi Wu ,  Buh-Kuan Fang

IPC分类号： H01L21/336

CPC分类号： H01L29/4232 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7833

摘要： A replacement gate process for fabricating a semiconductor device with metal gates includes forming a dummy gate stack, patterning dummy gates, doping source and drain regions for the gates, and forming an inter-level dielectric layer that overlays the source and drain regions. The sacrificial layer of the dummy gates is removed to form trenches using a three stage process. The first stage begins the trenches, whereby trenches entrance corners are exposed. The second stage is an etch that rounds the corners. The third stage is a main etch for the sacrificial layer, which is typically polysilicon. The corner rounding of the second stage improves the performance of the third stage and results in a better metal back fill including a reduction in pit defects. The process improves overall device yield in comparison to an otherwise equivalent process that omits the corner rounding step.

摘要翻译： 用于制造具有金属栅极的半导体器件的替代栅极工艺包括形成伪栅极堆叠，图案化伪栅极，用于栅极的掺杂源极和漏极区域，以及形成覆盖源极和漏极区域的层间电介质层。 去除伪栅极的牺牲层以使用三阶段工艺形成沟槽。 第一阶段开始沟渠，沟渠入口角落暴露。 第二阶段是一个刻蚀角落的蚀刻。 第三阶段是用于牺牲层的主要蚀刻，其通常是多晶硅。 第二阶段的圆角改善了第三阶段的性能，并且导致更好的金属回填，包括减少凹坑缺陷。 与省略角舍入步骤的其他等效过程相比，该过程提高了整体设备产量。

公开(公告)号：US20130105915A1

公开(公告)日：2013-05-02

申请号：US13286605

申请日：2011-11-01

申请人： Po-Chi WU ,  Ryan Chia-Jen CHEN

发明人： Po-Chi WU ,  Ryan Chia-Jen CHEN

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/02186 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

摘要翻译： 具有通过接触金属层的蚀刻溶液的组成确定的可选择阈值电压的金属氧化物半导体（MOS）器件。 MOS器件可以是p型或n型MOS，并且对于两种类型的MOS器件都可以选择阈值电压。 蚀刻溶液是含氧溶液或含氟化物溶液。 通过调节惰性气体进入蚀刻室的流量来控制阈值电压，以控制氧气或三氟化氮的浓度。