公开(公告)号：US09019140B2

公开(公告)日：2015-04-28

申请号：US14028244

申请日：2013-09-16

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract translation: 在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。 执行逐次逼近。 模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。 从模拟输入值中减去第一个模拟值，形成第一个残差。 量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。 然后将第二残基量化以形成第三量子化值。 第一，第二和第三量化值被转换为数字输出值。 第一，第二和第三量化值各自至少有三个等级。

公开(公告)号：US08928360B2

公开(公告)日：2015-01-06

申请号：US13854395

申请日：2013-04-01

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Wadeo Ou

IPC: H03K3/00 ,  H03G3/00 ,  H03G3/30

CPC classification number: H03G3/004 ,  H03G3/002 ,  H03G3/3089

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract translation: 实现功率高效的高频缓冲器的电路和方法。 检测缓冲信号的幅度并与输入信号的幅度进行比较。 比较结果可以反馈到数字控制缓冲器，以保持输出增益不变。 通过使用反馈控制，即使负载条件或信号频率变化，也可以将缓冲器保持在最合适的偏置状态。

公开(公告)号：US08729927B2

公开(公告)日：2014-05-20

申请号：US13657930

申请日：2012-10-23

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Ming Jiang ,  Jerry Cui

IPC: H03K3/00

CPC classification number: H03K17/102

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed

Abstract translation: 驱动电路包括具有设计最大电压V2的开关晶体管和具有设计最大电压V1的共源共栅晶体管，其中共源共栅晶体管是与开关晶体管串联耦合的源极 - 漏极。 电路还包括耦合在中间电压节点和共源共栅晶体管的栅极之间的电流源。 如果驱动电路是低端驱动器，则中间电压节点接收设置在高电源电压Vhigh以下的中间电压Vmed，并满足以下条件：a）Vmed <= V2和b）Vhigh-Vmed <= V1。 如果驱动电路是高侧驱动器，则中间电压节点接收低于高电源电压的中间电压Vmed，并且符合以下条件：a）Vmed <= V1和b）Vhigh-Vmed <= V2。 该电路可以通过将高侧驱动器和低侧驱动器串联耦合而构造为推挽驱动器。

公开(公告)号：US09000831B2

公开(公告)日：2015-04-07

申请号：US14073924

申请日：2013-11-07

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  KunKun Zheng

IPC: H03K17/687 ,  H03K17/10

CPC classification number: H03K17/102 ,  H03K2217/0054

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract translation: 通路电路包括耦合在输入节点（接收输入信号）和输出节点（输出输出信号）之间的第一晶体管。 第二晶体管被配置为响应于流过其中的偏置电流产生电压差，其中该电压差被施加在第一晶体管的第一栅极和输出节点之间。 差分放大器用于将输出节点处的电压与参考电压进行比较，并根据该比较产生偏置电流。

公开(公告)号：US08854106B2

公开(公告)日：2014-10-07

申请号：US13925032

申请日：2013-06-24

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  Snow Qi ,  Jackson Ding

IPC: H03K5/00 ,  H03K19/0185

CPC classification number: H03K19/018514

Abstract: A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.

Abstract translation: 电平移位电路包括产生第一偏置电流的电流镜和与第一偏置电流成比例的第二偏置电流。 第一电平移位器耦合在第一输入节点（接收第一输入信号）和耦合到当前反射镜的输入端的第一输出节点之间。 第一电平移位器响应于第一偏置电流向第一输入信号施加第一电压变化。 第二级耦合在第二输入节点（接收第二输入信号）和耦合到当前反射镜的输出端的第二输出节点之间。 第二电平移位器响应于第二偏置电流而将第二电压变化（与第一电压变化相关联）施加到第二输入信号。

公开(公告)号：US20140184305A1

公开(公告)日：2014-07-03

申请号：US14073924

申请日：2013-11-07

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei WANG ,  KunKun ZHENG

IPC: H03K17/10

CPC classification number: H03K17/102 ,  H03K2217/0054

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract translation: 通路电路包括耦合在输入节点（接收输入信号）和输出节点（输出输出信号）之间的第一晶体管。 第二晶体管被配置为响应于流过其中的偏置电流产生电压差，其中该电压差被施加在第一晶体管的第一栅极和输出节点之间。 差分放大器用于将输出节点处的电压与参考电压进行比较，并根据该比较产生偏置电流。

公开(公告)号：US20140015699A1

公开(公告)日：2014-01-16

申请号：US14028244

申请日：2013-09-16

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract translation: 在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。 执行逐次逼近。 模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。 从模拟输入值中减去第一个模拟值，形成第一个残差。 量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。 然后将第二残基量化以形成第三量子化值。 第一，第二和第三量化值被转换为数字输出值。 第一，第二和第三量化值各自至少有三个等级。

公开(公告)号：US20130222053A1

公开(公告)日：2013-08-29

申请号：US13854395

申请日：2013-04-01

Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.

Inventor： Jian Hua ZHAO ,  Wadeo Ou

IPC: H03G3/00

CPC classification number: H03G3/004 ,  H03G3/002 ,  H03G3/3089

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract translation: 实现功率高效的高频缓冲器的电路和方法。 检测缓冲信号的幅度并与输入信号的幅度进行比较。 比较结果可以反馈到数字控制缓冲器，以保持输出增益不变。 通过使用反馈控制，即使负载条件或信号频率变化，也可以将缓冲器保持在最合适的偏置状态。

公开(公告)号：US09000811B2

公开(公告)日：2015-04-07

申请号：US14199313

申请日：2014-03-06

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  Wen Li Bai

IPC: H03K3/00 ,  H03K17/04 ,  H03K17/00

CPC classification number: H03K17/00 ,  H03K17/163

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。

公开(公告)号：US20140266322A1

公开(公告)日：2014-09-18

申请号：US14199313

申请日：2014-03-06

Applicant: STMICROELECTRONICS R&D (SHANGHAI) CO. LTD.

Inventor： Fei Wang ,  Wen Li Bai

IPC: H03K3/012

CPC classification number: H03K17/00 ,  H03K17/163

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。