公开(公告)号：US07109779B2

公开(公告)日：2006-09-19

申请号：US11153355

申请日：2005-06-16

申请人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

发明人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

IPC分类号： H03L5/00

CPC分类号： H03K19/018585 ,  H03K19/01855

摘要： A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

摘要翻译： 半导体集成电路包括具有高于第一电路的击穿电压的第一电路和第二电路。 可以使第一和第二电路的工作电压彼此相等或不同。 第二电路具有电平移位电路，用于根据第二电路的操作电压来移位第一电路的输出信号的电平，外部输出缓冲器具有可以选择性地接收电平的输出信号的输入 移位电路或旁路电平移位电路的输入信号。 当第一和第二电路以低电压工作时，选择旁路。 在高压运行和老化期间，选择电平移位电路。

公开(公告)号：US20050231262A1

公开(公告)日：2005-10-20

申请号：US11153355

申请日：2005-06-16

申请人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

发明人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

IPC分类号： G01R31/30 ,  G01R31/28 ,  G01R31/316 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018585 ,  H03K19/01855

摘要： A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

摘要翻译： 半导体集成电路包括具有高于第一电路的击穿电压的第一电路和第二电路。 可以使第一和第二电路的工作电压彼此相等或不同。 第二电路具有电平移位电路，用于根据第二电路的操作电压来移位第一电路的输出信号的电平，外部输出缓冲器具有可以选择性地接收电平的输出信号的输入 移位电路或旁路电平移位电路的输入信号。 当第一和第二电路以低电压工作时，选择旁路。 在高压运行和老化期间，选择电平移位电路。

公开(公告)号：US20050206427A1

公开(公告)日：2005-09-22

申请号：US10912069

申请日：2004-08-06

申请人： Yuichi Yuasa ,  Shigemitsu Tahara ,  Daisuke Katagiri

发明人： Yuichi Yuasa ,  Shigemitsu Tahara ,  Daisuke Katagiri

IPC分类号： G06F15/78 ,  G11C5/00 ,  G11C11/16 ,  H01L21/822 ,  H01L27/04 ,  H03K5/1252

CPC分类号： G11C11/16

摘要： There is provided a semiconductor integrated circuit device that enables an EMS-voltage withstanding margin to be significantly enhanced without increasing a chip-layout area etc. An input buffer section, a CR filter composed of a resistor and an electrostatic capacitor device, a Schmitt circuit, and a noise cancellation circuit are connected to a system control terminal of the semiconductor integrated circuit device. When a signal containing noise is inputted to the system control terminal, a peak of the noise is reduced by an input buffer composed of the Schmitt circuit provided in the input buffer section. Thereafter, the peak of the noise is further reduced by the CR filter. Subsequently, the signal passes through the Schmitt circuit, thereby being significantly removed.

摘要翻译： 提供了一种半导体集成电路器件，其能够在不增加芯片布局面积等的情况下显着增强EMS耐压裕度。输入缓冲器部分，由电阻器和静电电容器器件组成的CR滤波器，施密特电路 ，并且噪声消除电路连接到半导体集成电路器件的系统控制端子。 当包含噪声的信号被输入到系统控制终端时，通过由输入缓冲器部分中提供的施密特电路组成的输入缓冲器来降低噪声的峰值。 此后，CR滤波器进一步降低了噪声的峰值。 随后，信号通过施密特电路，从而被明显地去除。

公开(公告)号：US06777997B2

公开(公告)日：2004-08-17

申请号：US10309183

申请日：2002-12-04

申请人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

发明人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

IPC分类号： H03L500

CPC分类号： H03K19/018585 ,  H03K19/01855

摘要： The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other. The second circuit has a plurality of level shift circuits capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit, a plurality of external output buffers receiving outputs of the level shift circuits, bypasses for bypassing an input of a predetermined level shift circuit to an input of a predetermined external output buffer, and a selecting circuit for selecting connection of either the predetermined level shift circuit or a bypass to an input of the predetermined external output buffer. In a use form in which the first and second circuits operate with a low voltage, the bypass is selected. In high-voltage operation and burn-in, the level shift circuits are selected.

摘要翻译： 从防止由于电平移位电路的输出操作延迟和维持输出缓冲器的高击穿电压的观点来看，本发明实现了与时钟信号同步的更高速的外部输出操作。 半导体集成电路包括具有比第一电路的击穿电压高的击穿电压的第一电路和第二电路，并且可以使第一和第二电路的操作电压彼此相等或不同。 第二电路具有多个电平移位电路，能够根据第二电路的工作电压来移动第一电路的输出电平，接收电平移位电路的输出的多个外部输出缓冲器，用于旁路的旁路 将预定电平移位电路输入到预定的外部输出缓冲器的输入端，以及选择电路，用于选择预定电平移位电路或旁路中的任一者与预定外部输出缓冲器的输入端的连接。 在第一和第二电路以低电压工作的使用形式中，选择旁路。 在高压运行和老化期间，选择电平移位电路。