公开(公告)号：US20080276020A1

公开(公告)日：2008-11-06

申请号：US12177747

申请日：2008-07-22

Applicant: Michael Ching ,  Steven Woo

Inventor： Michael Ching ,  Steven Woo

IPC: G06F13/38

CPC classification number: G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Abstract translation: 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US20050165970A1

公开(公告)日：2005-07-28

申请号：US10766334

申请日：2004-01-28

Applicant: Michael Ching ,  Steven Woo

Inventor： Michael Ching ,  Steven Woo

IPC: G06F3/00 ,  G06F13/40 ,  H04L5/14 ,  H04L5/18 ,  H04L25/02

CPC classification number: G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Abstract translation: 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US20050060533A1

公开(公告)日：2005-03-17

申请号：US10664762

申请日：2003-09-17

Applicant: Steven Woo ,  Bradley May ,  Rong Fang

Inventor： Steven Woo ,  Bradley May ,  Rong Fang

IPC: G06F1/24 ,  G06F12/02

CPC classification number: G06F12/0215 ,  Y02D10/13

Abstract: Embodiments of the present invention allow a method, device, software and apparatus to adjust a system parameter, such as a page closing time value, in order to enhance a processing device performance. For example, a method includes initializing a page closing time value by a BIOS software component. A processing device, such as a computer, operates responsive to the page closing time value. For example, the computer executes a graphic display software program. An operational value, such as a difference between page hits and page misses, is obtained while executing the software program and compared to a threshold value. The page closing time value is then adjusted responsive to the comparison. In an alternate embodiment of the present invention, an adaptive circuit is included in a memory controller and includes a first counter capable to obtain a number of page hits and a second counter capable to obtain a number of page misses. Comparator logic is coupled to the first and second counters and outputs a page closing time adjust signal.

Abstract translation: 本发明的实施例允许方法，设备，软件和装置来调整诸如页面关闭时间值的系统参数，以便增强处理设备的性能。 例如，一种方法包括通过BIOS软件组件初始化页面关闭时间值。 诸如计算机的处理设备响应于页面关闭时间值而进行操作。 例如，计算机执行图形显示软件程序。 在执行软件程序并与阈值进行比较时获得操作值，例如页面命中和页面错误之间的差异。 响应于比较来调整页面关闭时间值。 在本发明的替代实施例中，自适应电路被包括在存储器控制器中，并且包括能够获得多个页面命中的第一计数器和能够获得多个页错失的第二计数器。 比较器逻辑耦合到第一和第二计数器并输出页面关闭时间调整信号。

公开(公告)号：US08149874B2

公开(公告)日：2012-04-03

申请号：US13110217

申请日：2011-05-18

Applicant: Michael Ching ,  Steven Woo

Inventor： Michael Ching ,  Steven Woo

IPC: H04J3/16

CPC classification number: G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Abstract translation: 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US08073009B2

公开(公告)日：2011-12-06

申请号：US12177747

申请日：2008-07-22

Applicant: Michael Ching ,  Steven Woo

Inventor： Michael Ching ,  Steven Woo

IPC: H04J3/16

CPC classification number: G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Abstract translation: 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US07755968B2

公开(公告)日：2010-07-13

申请号：US11834915

申请日：2007-08-07

Applicant: Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

Inventor： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

IPC: G11C8/00

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

Abstract: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

Abstract translation: 集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。 存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸 第二种操作模式。 存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

公开(公告)号：US20050262323A1

公开(公告)日：2005-11-24

申请号：US10850803

申请日：2004-05-21

Applicant: Steven Woo ,  Brian Tsang

Inventor： Steven Woo ,  Brian Tsang

IPC: G06F12/00 ,  G06F13/16 ,  G11C7/00

CPC classification number: G06F13/161 ,  G06F13/1631

Abstract: A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.

Abstract translation: 具有多个存储器件的存储器系统通过为不同的物理存储器区域启用不同的延迟来降低平均访问等待时间，从而提供有助于将频繁访问的存储器地址放置到物理存储器的最低延迟区域中的地址映射; 以及将经常访问的存储器地址分配给物理存储器的最低延迟区域。

公开(公告)号：US07454555B2

公开(公告)日：2008-11-18

申请号：US10865398

申请日：2004-06-10

Applicant: Frederick A. Ware ,  Ely Tsern ,  Steven Woo ,  Richard E. Perego

Inventor： Frederick A. Ware ,  Ely Tsern ,  Steven Woo ,  Richard E. Perego

IPC: G06F12/00

CPC classification number: G11C11/413 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12

Abstract: An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive fast-cycle, fixed latency single memory device. In an embodiment of the invention, a memory controller includes controller logic and a plurality of write buffers for interleaving write transactions to each memory bank in the two memory devices. A memory controller also includes tag memory for identifying valid data in the memory banks. In another embodiment of the invention, a game console includes the apparatus and executes game software that requires fixed latency in a mode of operation. In yet another embodiment of the invention, each memory device is coupled to respective write channels. Write data is simultaneously written to two memory banks in respective sets of memory banks in a memory device in an embodiment of the present invention. In an alternate embodiment of the present invention, an apparatus includes four memory devices for storing duplicate data with each memory device having a set of memory banks. The four memory devices are coupled to a controller by four respective write channels.

Abstract translation: 在本发明的实施例中，一种装置包括用于在每个存储体中存储重复数据的两个多存储体存储器件。 两个存储器件能够替代更昂贵的快速循环，固定延迟单个存储器件。 在本发明的实施例中，存储器控制器包括控制器逻辑和用于将写入事务交织到两个存储器件中的每个存储体的多个写入缓冲器。 存储器控制器还包括用于识别存储体中的有效数据的标签存储器。 在本发明的另一个实施例中，游戏机包括该装置并执行在操作模式中需要固定等待时间的游戏软件。 在本发明的另一个实施例中，每个存储器件耦合到相应的写入通道。 在本发明的一个实施例中，写入数据被同时写入存储器装置中相应存储体组中的两个存储体。 在本发明的替代实施例中，一种装置包括四个用于存储与具有一组存储器组的每个存储器件重复数据的存储器件。 四个存储器件通过四个相应的写通道耦合到控制器。

公开(公告)号：US20070204036A1

公开(公告)日：2007-08-30

申请号：US11799408

申请日：2007-04-30

Applicant: Shai Mohaban ,  Steven Woo

Inventor： Shai Mohaban ,  Steven Woo

IPC: G06F15/173

CPC classification number: H04L12/66

Abstract: Techniques for creating policies for use in policy-based management of quality of service treatments of network data traffic flows are described. Policies are defined based on information about types of flows generated by an application and quality of service functions that are available in the network. Application information is received that defines flows generated by an application, including points where the application generates the traffic flows. QoS information is received that defines one of more quality of service treatments that the network device may apply to data processed by the network device. Based on the information, processing policies that associate the flows with the QoS treatments are determined. Mappings of the application information to the QoS treatments, which may be used to generate the quality of service value when the application program generates flows, are created and stored. Thus, the policies are informed both by application expertise and network expertise.

Abstract translation: 描述了用于创建用于网络数据业务流的服务质量处理的策略管理策略的技术。 基于由应用程序生成的流程类型和网络中可用的服务质量的信息定义策略。 收到定义应用程序生成的流的应用程序信息，包括应用程序生成流量的点。 接收到QoS信息，其定义了网络设备可以应用于由网络设备处理的数据的更多服务质量的治疗之一。 基于该信息，确定将流与QoS处理相关联的处理策略。 创建并存储应用程序生成流时可用于生成服务质量值的QoS处理的应用信息的映射。 因此，政策通过应用专长和网络专业知识获得通知。

公开(公告)号：US20060067146A1

公开(公告)日：2006-03-30

申请号：US10954941

申请日：2004-09-30

Applicant: Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

Inventor： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

IPC: G11C7/02

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

Abstract translation: 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。