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1.发明申请Integrated circuit memory system having dynamic memory bank count and page size 有权具有动态存储体积和页面大小的集成电路存储器系统公开(公告)号：US20060067146A1
公开(公告)日：2006-03-30
申请号：US10954941
申请日：2004-09-30
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。
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2.发明申请Integrated Circuit Memory Device Having Dynamic Memory Bank Count and Page Size 有权具有动态存储器计数和页面大小的集成电路存储器件公开(公告)号：US20070268765A1
公开(公告)日：2007-11-22
申请号：US11834915
申请日：2007-08-07
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.
摘要翻译： 集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。 存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸 第二种操作模式。 存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。
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3.发明授权DRAM output circuitry supporting sequential data capture to reduce core access times 失效DRAM输出电路支持顺序数据采集，以减少核心访问时间公开(公告)号：US06754120B1
公开(公告)日：2004-06-22
申请号：US10364178
申请日：2003-02-11
申请人： Chad Bellows , Wayne Richardson , Lawrence Lai , Kurt Knorpp
发明人： Chad Bellows , Wayne Richardson , Lawrence Lai , Kurt Knorpp
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/06 , G11C7/1012 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C11/4096
摘要： Described are memory systems designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both.
摘要翻译： 描述了旨在强调存储单元访问时间之间的差异的存储器系统。 作为这些访问时间变化的结果，从不同存储器单元读取的数据到达一些修改的输出电路。 输出电路按顺序卸载数据。 数据访问时间减少，因为输出电路可以在较慢的数据准备好捕捉之前开始移位第一个数据到达。 可以使用不同大小的读出放大器，路由或两者来强调给定存储器阵列中的单元的数据访问时间之间的差异。
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公开(公告)号：US20050237094A1
公开(公告)日：2005-10-27
申请号：US11148783
申请日：2005-06-08
申请人： Donald Stark , Jun Kim , Kurt Knorpp , Michael Ching , Natsuki Kushiyama
发明人： Donald Stark , Jun Kim , Kurt Knorpp , Michael Ching , Natsuki Kushiyama
IPC分类号： G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译： 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出q-节点信号。 输出电流5河接收q节点信号，并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。
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公开(公告)号：US20050248383A1
公开(公告)日：2005-11-10
申请号：US11123225
申请日：2005-05-06
申请人： Wayne Fang , Wayne Richardson , Kurt Knorpp
发明人： Wayne Fang , Wayne Richardson , Kurt Knorpp
IPC分类号： H03B1/00 , H03K3/00 , H03K17/693
CPC分类号： H03K17/693
摘要： A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.
摘要翻译： 公开了脉冲多路复用输出子系统。 在一个特定示例性实施例中，输出子系统可以包括多个脉冲发生器，第一对晶体管和第二对晶体管，其中第一对晶体管中的每一个耦合到第一对晶体管中的相应一个 多个脉冲发生器，并且其中第二对晶体管中的每一个耦合到第二对多个脉冲发生器中的相应一个。 输出子系统还可以包括第一对电阻负载，其中第一对电阻负载中的每一个耦合到第一对晶体管中的相应一个和第二对晶体管中的相应一个，以及第一电流源 耦合到第一对晶体管和第二对晶体管。
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公开(公告)号：US5327382A
公开(公告)日：1994-07-05
申请号：US942627
申请日：1992-09-09
申请人： Katsunori Seno , Kurt Knorpp
发明人： Katsunori Seno , Kurt Knorpp
CPC分类号： G11C29/24
摘要： In a single chip semiconductor memory, having independent memory areas for normal memory cells and redundant memory cells, the redundant cells are tested in a parallel or multi-bit test mode simultaneously with the normal cells they replace, by enabling the redundant memory area in response to simultaneous detection of the state of the multi-bit test mode, the presence of a programmed redundant bit for a memory cell under test, and the operative selection of the normal memory matrix.
摘要翻译： 在具有用于正常存储器单元和冗余存储器单元的独立存储器区域的单芯片半导体存储器中，通过使冗余存储器区域响应，冗余单元以并行或多位测试模式与其所代替的正常单元同时测试 同时检测多位测试模式的状态，存在用于被测存储单元的编程冗余位和正常存储器矩阵的可操作选择。
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公开(公告)号：US5519712A
公开(公告)日：1996-05-21
申请号：US323053
申请日：1994-10-12
申请人： Lee-Lean Shu , Kurt Knorpp , Katsunori Seno
发明人： Lee-Lean Shu , Kurt Knorpp , Katsunori Seno
IPC分类号： G01R31/28 , G11C11/413 , G11C29/34 , G11C29/38 , G11C29/00
CPC分类号： G11C29/38
摘要： A test circuit for a single chip semiconductor memory array, located in the chip, enables testing of all columns along a word lines without additional column readout circuits. A pair of current detecting differential amplifiers are connected to the bit lines of multiple memory cells along a word line, and the amplifier outputs are compared to generate a pass/fail signal during a read access.
摘要翻译： 位于芯片中的单芯片半导体存储器阵列的测试电路使得能够沿着字线测试所有列，而不需要附加的列读出电路。 一对电流检测差分放大器沿着字线连接到多个存储器单元的位线，并且在读取访问期间比较放大器输出以产生通过/失败信号。
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8.发明授权
公开(公告)号：US5457407A
公开(公告)日：1995-10-10
申请号：US268118
申请日：1994-07-06
申请人： Lee-Lean Shu , Kurt Knorpp
发明人： Lee-Lean Shu , Kurt Knorpp
IPC分类号： H03H7/38 , H03K17/12 , H03K17/687 , H03K19/00 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/0005
摘要： An output buffer comprises a reference circuit having a plurality of reference transistors connected in parallel to each other and a output driver circuit having a corresponding plurality of driver transistors connected in parallel with each other. The reference transistors and the driver transistors both have varying widths with the widths of the reference transistors being a binary fraction, for instance one fourth, smaller than the widths of the corresponding output driver transistors. The transistors in the reference circuit are selectively conducted in order to match an impedance of the reference transistors to the impedance of a user selected resistor, representing a fraction of the impedance of a transmission line. The selection of the reference transistors also determines the selection of the driver transistors and consequently causes the impedance of the output driver to match the impedance of the transmission line. The reduction of the reference circuit by the binary fraction reduces the size of the overall circuit, lowers power consumption, and allows a matched layout between the transistors of the output driver and the reference circuit.
摘要翻译： 输出缓冲器包括具有彼此并联连接的多个参考晶体管的参考电路和具有彼此并联连接的相应多个驱动晶体管的输出驱动器电路。 参考晶体管和驱动器晶体管都具有变化的宽度，参考晶体管的宽度是二进制分数，例如比对应的输出驱动晶体管的宽度小四分之一。 参考电路中的晶体管被选择性地导通，以便将参考晶体管的阻抗与用户选择的电阻器的阻抗相匹配，代表传输线的阻抗的一部分。 参考晶体管的选择也决定了驱动晶体管的选择，从而使输出驱动器的阻抗匹配传输线的阻抗。 通过二进制分数的参考电路的减少减小了整个电路的尺寸，降低了功耗，并且允许输出驱动器和参考电路的晶体管之间的匹配布局。
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公开(公告)号：US09111645B2
公开(公告)日：2015-08-18
申请号：US13000280
申请日：2009-07-17
CPC分类号： G11C29/16 , G11C29/028 , G11C29/12015 , G11C29/18 , G11C29/56012
摘要： Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.
摘要翻译： 描述存储器件的实施例。 该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。 给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。 此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。
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公开(公告)号：US20110126081A1
公开(公告)日：2011-05-26
申请号：US13000280
申请日：2009-07-17
CPC分类号： G11C29/16 , G11C29/028 , G11C29/12015 , G11C29/18 , G11C29/56012
摘要： Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.
摘要翻译： 描述存储器件的实施例。 该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。 给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。 此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。
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