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1.发明授权System and method for identifying and managing service disruptions using network and systems data 有权使用网络和系统数据识别和管理服务中断的系统和方法公开(公告)号：US08305911B2
公开(公告)日：2012-11-06
申请号：US12431040
申请日：2009-04-28
申请人： Kiran P. Diwakar , Sumeet Mathur
发明人： Kiran P. Diwakar , Sumeet Mathur
CPC分类号： G06F11/34 , H04L41/147
摘要： A method for identifying disruptions using network and systems data includes receiving resource utilization information for a network component at a first time and receiving resource utilization information for the network component at a second time. The method also includes identifying a resource utilization pattern for the network component, predicting a resource utilization for the network component at a third time based on the resource utilization pattern, and determining whether the predicted resource utilization will breach a utilization threshold for the network component.
摘要翻译： 用于使用网络和系统数据识别中断的方法包括在第一时间接收网络组件的资源利用信息，并在第二时间接收网络组件的资源利用信息。 该方法还包括识别网络组件的资源利用模式，基于资源利用模式，在第三时间预测网络组件的资源利用率，以及确定预测的资源利用率是否会破坏网络组件的利用率阈值。
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2.发明申请CAPACITOR BASED DIGITAL TO ANALOG CONVERTER LAYOUT DESIGN FOR HIGH SPEED ANALOG TO DIGITAL CONVERTER 有权基于电容器的数字转换器用于高速模拟数字转换器的模拟转换器布局设计公开(公告)号：US20100253563A1
公开(公告)日：2010-10-07
申请号：US12729291
申请日：2010-03-23
CPC分类号： H03M1/0612 , H01L27/0207 , H03M1/68 , H03M1/804
摘要： A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates to form the capacitor. Each of the plurality of metal plates includes a driven plate and a common plate. The method also includes generating a plurality of interconnects in the common plate and extending the driven plate over the plurality of interconnects. Further, the method includes shielding the common plate by the driven plate. The system includes an analog to digital converter. The analog to digital converter also includes capacitor based digital to analog converter and digital logic for controlling digital operations in the analog to digital converter. The capacitor based digital to analog converter includes a plurality of capacitors, and a comparator for comparing the analog output from the digital to analog converter with a ground potential.
摘要翻译： 提供了一种用于高速模数转换器的基于电容器的数模转换器设计布局的方法和系统。 该方法包括布置多个金属板以形成电容器。 多个金属板中的每一个包括从动板和公共板。 该方法还包括在公共板中产生多个互连件并且在多个互连件上延伸从动板。 此外，该方法包括通过从动板屏蔽公共板。 该系统包括一个模数转换器。 模数转换器还包括基于电容的数模转换器和用于控制模数转换器中的数字操作的数字逻辑。 基于电容器的数模转换器包括多个电容器，以及用于将来自数模转换器的模拟输出与地电势进行比较的比较器。
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3.发明授权Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity 有权在降低维持线性的同时驱动采样和保持电路的放大级中降低功耗公开(公告)号：US07724042B2
公开(公告)日：2010-05-25
申请号：US11774017
申请日：2007-07-06
IPC分类号： H03K5/00
CPC分类号： G11C27/026
摘要： An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption.
摘要翻译： 由采样和保持电路采样的输入信号由两个放大器单独放大。 第一放大器的输出被提供给升压电路，以维持包含在信号相关升压开关中的采样开关的阻抗基本恒定。 通过采样开关对第二放大器的输出进行采样，样品存储在存储元件中。 第二放大器驱动减小的负载，并且可以被实现为低带宽低功率放大器以降低整体功耗。
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公开(公告)号：US08648646B2
公开(公告)日：2014-02-11
申请号：US13301778
申请日：2011-11-22
申请人： Anand Mohan , Sumeet Mathur
发明人： Anand Mohan , Sumeet Mathur
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： An electrical system for generating arbitrary voltage waveform includes a power supply unit for providing a supply voltage to the electrical system. One or more charge pumps are in electrical communication with the power supply unit. Each charge pump generates a voltage. The electrical system also includes a plurality of switches, a first switch among the plurality of switches coupled between a ground and an output terminal, other switches among the plurality of switches coupled between the one or more charge pumps and the output terminal. A control circuit is in electrical communication with the power supply unit, the plurality of switches and the one or more charge pumps, and is operable to control the voltage generated by the each charge pump and the plurality of switches. Voltages from the one or more charge pumps additively result in a variable output voltage that generates an arbitrary voltage waveform.
摘要翻译： 用于产生任意电压波形的电气系统包括用于向电气系统提供电源电压的电源单元。 一个或多个电荷泵与电源单元电连通。 每个电荷泵产生一个电压。 电气系统还包括多个开关，耦合在地和输出端之间的多个开关中的第一开关，耦合在一个或多个电荷泵与输出端之间的多个开关中的其它开关。 控制电路与电源单元，多个开关和一个或多个电荷泵电连通，并且可操作以控制由每个电荷泵和多个开关产生的电压。 来自一个或多个电荷泵的电压相加地导致产生任意电压波形的可变输出电压。
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公开(公告)号：US07868688B2
公开(公告)日：2011-01-11
申请号：US12463389
申请日：2009-05-09
IPC分类号： H03K5/00
CPC分类号： H03F3/345
摘要： A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.
摘要翻译： 提供电流滤波电路。 电流滤波器电路包括源极晶体管，源极晶体管包括漏极，栅极和源极。 源极晶体管的源极耦合到参考电压端子，源极晶体管的栅极耦合到反射镜晶体管的栅极，源极晶体管的漏极耦合到参考电流源。 反射镜晶体管包括漏极，栅极和源极。 反射镜晶体管的源极耦合到参考电压端子，栅极耦合到源极晶体管的栅极，并且漏极耦合到负载。 电流滤波电路包括用于滤除噪声的低通滤波器。 电流滤波器电路还包括耦合到镜晶体管的漏极的阻抗减小电路，用于减小电流滤波器电路的带宽。
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6.发明申请System and Method for Identifying and Managing Service Disruptions Using Network and Systems Data 有权使用网络和系统数据识别和管理服务中断的系统和方法公开(公告)号：US20100271956A1
公开(公告)日：2010-10-28
申请号：US12431040
申请日：2009-04-28
申请人： Kiran P. Diwakar , Sumeet Mathur
发明人： Kiran P. Diwakar , Sumeet Mathur
IPC分类号： H04J3/22
CPC分类号： G06F11/34 , H04L41/147
摘要： A method for identifying disruptions using network and systems data includes receiving resource utilization information for a network component at a first time and receiving resource utilization information for the network component at a second time. The method also includes identifying a resource utilization pattern for the network component, predicting a resource utilization for the network component at a third time based on the resource utilization pattern, and determining whether the predicted resource utilization will breach a utilization threshold for the network component.
摘要翻译： 用于使用网络和系统数据识别中断的方法包括在第一时间接收网络组件的资源利用信息，并在第二时间接收网络组件的资源利用信息。 该方法还包括识别网络组件的资源利用模式，基于资源利用模式，在第三时间预测网络组件的资源利用率，以及确定预测的资源利用率是否会破坏网络组件的利用率阈值。
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公开(公告)号：US20100164611A1
公开(公告)日：2010-07-01
申请号：US12463389
申请日：2009-05-09
IPC分类号： H03B1/00
CPC分类号： H03F3/345
摘要： A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.
摘要翻译： 提供电流滤波电路。 电流滤波器电路包括源极晶体管，源极晶体管包括漏极，栅极和源极。 源极晶体管的源极耦合到参考电压端子，源极晶体管的栅极耦合到反射镜晶体管的栅极，源极晶体管的漏极耦合到参考电流源。 反射镜晶体管包括漏极，栅极和源极。 反射镜晶体管的源极耦合到参考电压端子，栅极耦合到源极晶体管的栅极，并且漏极耦合到负载。 电流滤波电路包括用于滤除噪声的低通滤波器。 电流滤波器电路还包括耦合到镜晶体管的漏极的阻抗减小电路，用于减小电流滤波器电路的带宽。
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公开(公告)号：US06611163B1
公开(公告)日：2003-08-26
申请号：US10102291
申请日：2002-03-20
申请人： Subhashish Mukherjee , Sourja Ray , Sumeet Mathur
发明人： Subhashish Mukherjee , Sourja Ray , Sumeet Mathur
IPC分类号： G06G764
CPC分类号： H03F3/45977 , G01R19/0023 , H03F3/005 , H03K5/2481 , H03K5/249
摘要： An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage amplifier 62. The comparator 70 also includes additional capacitors 82 and 83 coupled between the inputs of the preamplifier 78 and reference voltage nodes VREFP and VREFM. Switches 73 and 74 are coupled between the additional capacitors 82 and 83 and the reference voltage nodes VREFP and VREFM. An additional switch 72 is coupled between the additional capacitors 82 and 83. In this configuration, there are no series sampling switches between the previous stage amplifier 62 and the comparator 70. Eliminating the series switches reduces the load seen by the previous stage amplifier 62, which allows the previous stage amplifier 62 to have a faster settling time. This allows the current in the previous stage amplifier 62 to be decreased which reduces the power consumption.
摘要翻译： 偏移补偿比较器70具有直接耦合在前置放大器78的输入端和前一级放大器62的输出之间的电容器80和81.比较器70还包括耦合在前置放大器78的输入端和参考电压之间的附加电容器82和83 节点VREFP和VREFM。 开关73和74耦合在附加电容器82和83与参考电压节点VREFP和VREFM之间。 附加开关72耦合在附加电容器82和83之间。在该配置中，在前级放大器62和比较器70之间不存在串联采样开关。消除串联开关减小了前级放大器62所看到的负载， 这允许前级放大器62具有更快的建立时间。 这允许降低前级放大器62中的电流，从而降低功耗。
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公开(公告)号：US08106706B2
公开(公告)日：2012-01-31
申请号：US12463390
申请日：2009-05-09
摘要： A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.
摘要翻译： 用于偏置MOS晶体管的方法包括将来自放大器级的输入信号AC耦合到MOS晶体管的栅极。 该方法包括将一对相反并联配置的二极管连接到偏置晶体管和电流源。 此外，该方法包括通过偏置晶体管和电流源产生DC偏置电压。 该方法还包括通过钳位电路将偏置晶体管的漏极处的电压钳位到固定电压。 此外，该方法包括通过一对二极管将DC偏置电压耦合到MOS晶体管的栅极。
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10.发明授权公开(公告)号：US07629910B2
公开(公告)日：2009-12-08
申请号：US11864979
申请日：2007-09-29
申请人： Sriram Ramadoss , Sumeet Mathur
发明人： Sriram Ramadoss , Sumeet Mathur
IPC分类号： H03M1/00
CPC分类号： H03M1/0881 , H03M1/747
摘要： Methods and apparatus to control current steering digital to analog converters are described herein. In one example, a digital to analog converter includes a first unit cell including a positive output and a negative output, wherein the positive output of the first unit cell and the negative output of the first unit cell comprise substantially equal magnitudes and wherein the positive and negative outputs of the first unit cell are substantially one hundred eighty degrees out of phase; and a second unit cell including a positive output and a negative output, wherein the positive output of the second unit cell is substantially zero when the negative output of the second unit cell is non-zero.
摘要翻译： 本文描述了控制电流转向数模转换器的方法和装置。 在一个示例中，数模转换器包括包括正输出和负输出的第一单元，其中第一单元的正输出和第一单元的负输出包括基本上相等的幅度，并且其中正和 第一单元的负输出基本上相差一百八十度; 以及包括正输出和负输出的第二单元，其中当所述第二单元的负输出不为零时，所述第二单元的正输出基本为零。
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