公开(公告)号：US20180048325A1

公开(公告)日：2018-02-15

申请号：US15234741

申请日：2016-08-11

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： Edmund Mark SCHNEIDER ,  Daniel J. ALLEN ,  Saurabh SINGH ,  Aniruddha SATOSKAR

IPC分类号： H03M1/12 ,  G06F13/42 ,  G06F13/40

CPC分类号： H03M1/12 ,  G06F13/4022 ,  G06F13/4282 ,  H03M1/0872 ,  H03M1/0881 ,  H03M1/188

摘要： In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths and a controller. The plurality of processing paths may include a static processing path configured to generate a first digital signal based on an analog input signal and a dynamic processing path configured to generate a second digital signal based on the analog input signal, wherein a parameter of the dynamic processing path is determined based on a characteristic of the analog input signal. The controller may be configured to select the first digital signal as a digital output signal of the processing system when a change is occurring to the characteristic and select the second digital signal as the digital output signal in the absence of change occurring to the characteristic.

公开(公告)号：US09484946B2

公开(公告)日：2016-11-01

申请号：US14468078

申请日：2014-08-25

申请人： NXP B.V.

发明人： Mattieu Deloge ,  Arnoud Pieter van der Wel

IPC分类号： H04B1/38 ,  H03M1/66 ,  H03M1/08 ,  H03M1/74

CPC分类号： H03M1/661 ,  H03M1/0881 ,  H03M1/745 ,  H04B1/38

摘要： Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.

摘要翻译： 描述了数模转换器（DAC）的实施例，用于操作DAC的方法和收发器电路。 在一个实施例中，DAC包括被配置为接收数字信号的输入端子，被配置为使用允许低电磁发射的一阶插值将数字信号转换成模拟信号的转换器电路，以及被配置为输出模拟信号的输出端子 。 还描述了其它实施例。

公开(公告)号：US09178524B1

公开(公告)日：2015-11-03

申请号：US14493254

申请日：2014-09-22

申请人： QUALCOMM Incorporated

发明人： Sang Min Lee ,  Dongwon Seo

IPC分类号： H03M1/66 ,  H03M1/08 ,  H03M1/68 ,  H03M1/78

CPC分类号： H03M1/0863 ,  H03M1/0612 ,  H03M1/0881 ,  H03M1/687 ,  H03M1/785

摘要： The apparatus may be an N-bit DAC including (2M−1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M−1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.

摘要翻译： 该装置可以是包括与M个最高有效位相关联的（2M-1）个并行级和与（N-M）个最低有效位相关联的（N-M）级的N位DAC。 （2M-1）并联级可以将第一电流传送到DAC的电流求和节点。 （N-M）级可以包括电阻网络和第二对开关，并且可以将第二电流传递到级的电阻网络。 每个电阻网络可以根据对应于电阻网络的级的二进制权重来缩放分别传递的电流，并且可以将缩放的电流传送到一对电流求和节点。 （N-M）级中的至少一个可以与其余级分离。

公开(公告)号：US08547160B2

公开(公告)日：2013-10-01

申请号：US13712522

申请日：2012-12-12

申请人： Fujitsu Semiconductor Limited

发明人： Ian Juso Dedic ,  Gavin Lambertus Allen

IPC分类号： H03K17/00

CPC分类号： H03M1/0614 ,  G11C27/02 ,  H01H9/54 ,  H03K17/00 ,  H03L7/00 ,  H03L7/091 ,  H03M1/002 ,  H03M1/0881 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/126 ,  Y10T307/76

摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

公开(公告)号：US07869388B2

公开(公告)日：2011-01-11

申请号：US12800959

申请日：2010-05-26

申请人： Ramsin Michael Ziazadeh ,  Varadarajan Devnath

发明人： Ramsin Michael Ziazadeh ,  Varadarajan Devnath

IPC分类号： H04B1/56 ,  H03M1/66

CPC分类号： H04L25/0266 ,  H03M1/0881 ,  H03M1/742

摘要： A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

摘要翻译： 一种用于千兆以太网收发器的方法和装置，其在主发射机中具有B类放大器以实现更高的效率和功率处理能力。 主发射机的输出电流由施加在电阻器上的参考电压产生，其中参考电压发生器，电阻器和放大器被制造在同一衬底上，使得输出电流在过程电压和温度之间是恒定的。 收发器还具有一个复制发射机，其信号用于在收发机的接收机部分的输入处取消主发射机信号。 复制发射机制造在与主发射机相同的衬底上，使得其输出信号反映主发射机中跨过程电压和温度的非线性。

公开(公告)号：US07629910B2

公开(公告)日：2009-12-08

申请号：US11864979

申请日：2007-09-29

申请人： Sriram Ramadoss ,  Sumeet Mathur

发明人： Sriram Ramadoss ,  Sumeet Mathur

IPC分类号： H03M1/00

CPC分类号： H03M1/0881 ,  H03M1/747

摘要： Methods and apparatus to control current steering digital to analog converters are described herein. In one example, a digital to analog converter includes a first unit cell including a positive output and a negative output, wherein the positive output of the first unit cell and the negative output of the first unit cell comprise substantially equal magnitudes and wherein the positive and negative outputs of the first unit cell are substantially one hundred eighty degrees out of phase; and a second unit cell including a positive output and a negative output, wherein the positive output of the second unit cell is substantially zero when the negative output of the second unit cell is non-zero.

摘要翻译： 本文描述了控制电流转向数模转换器的方法和装置。 在一个示例中，数模转换器包括包括正输出和负输出的第一单元，其中第一单元的正输出和第一单元的负输出包括基本上相等的幅度，并且其中正和 第一单元的负输出基本上相差一百八十度; 以及包括正输出和负输出的第二单元，其中当所述第二单元的负输出不为零时，所述第二单元的正输出基本为零。

公开(公告)号：US20050195991A1

公开(公告)日：2005-09-08

申请号：US10862917

申请日：2004-06-07

申请人： Yuhe Wang ,  Peter White ,  Daniel Ho ,  Frank Nguyen ,  Chin-Chi Chang ,  Jeetin Rathore

发明人： Yuhe Wang ,  Peter White ,  Daniel Ho ,  Frank Nguyen ,  Chin-Chi Chang ,  Jeetin Rathore

IPC分类号： H02B1/00 ,  H04B15/00

CPC分类号： H03F1/305 ,  H03F3/187 ,  H03G3/002 ,  H03M1/0881 ,  H03M1/66

摘要： A method and system are disclosed for controlling pop noises in a sound broadcasting system. After controllably connecting an output of a drive amplifier to a first predetermined low voltage level through a first switch, a first portion of an operation control data set is input to a digital-to-analog converter (DAC) circuit for driving an output thereof to a second predetermined low voltage level, and a second portion of the operation control data set is also input to the DAC circuit and further to the drive amplifier to bring the output of the drive amplifier to a common mode voltage level over a predetermined rise-up time period for controlling the pop noises.

摘要翻译： 公开了一种用于控制声音广播系统中的弹奏噪声的方法和系统。 在通过第一开关可控地将驱动放大器的输出连接到第一预定低电压电平之后，操作控制数据组的第一部分被输入到数模转换器（DAC）电路，用于驱动其输出到 第二预定低电压电平和第二部分操作控制数据组也被输入到DAC电路，并进一步输入到驱动放大器，以使驱动放大器的输出达到预定上升沿的共模电压电平 控制流行音色的时间段。

公开(公告)号：US20050073452A1

公开(公告)日：2005-04-07

申请号：US10947646

申请日：2004-09-22

申请人： Gabriele Manganaro

发明人： Gabriele Manganaro

IPC分类号： H03M1/72 ,  H03M1/66

CPC分类号： H03M1/0881 ,  H03M1/72

摘要： The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

摘要翻译： 通过平衡其预充电开关的稳定特性，开关电容器，管线数模转换器的线性度得到改善。 更详细地，开关电容器DAC包括多个基本上相同的单元，输入数字字的每个位的一个单元。 使用多个开关驱动器电路来施加相应的开关控制信号以打开和关闭相应的开关。 有利的是，开关控制信号的差异被确定为均衡不同开关之间的栅极 - 源极电压差。

公开(公告)号：US20030043062A1

公开(公告)日：2003-03-06

申请号：US10158918

申请日：2002-06-03

申请人： FUJITSU LIMITED

发明人： Ian Juso Dedic ,  Darren Walker

IPC分类号： H03M001/66

CPC分类号： H03M1/0881 ,  H03M1/747

摘要： Segmented mixed signal circuitry comprising a plurality of analog segments is disclosed. Each analog segment is operable to perform a series of switching operations dependent on an input data signal. The circuitry is arranged to receive shaped clock signals provided in common for all segments, and to perform each switching operation in a manner determined by the shape of the common shaped clock signals. The circuitry is suitable for use in digital to analog converters (DACs).

摘要翻译： 公开了包括多个模拟段的分段混合信号电路。 每个模拟段可操作以执行依赖于输入数据信号的一系列切换操作。 电路被布置为接收为所有段共同提供的成形时钟信号，并且以由共同形状的时钟信号的形状确定的方式执行每个切换操作。 该电路适用于数模转换器（DAC）。

公开(公告)号：US20020000929A1

公开(公告)日：2002-01-03

申请号：US09897325

申请日：2001-07-02

发明人： Matthew Cushman ,  Aleksander Ignjatovic

IPC分类号： H03M001/12

CPC分类号： H03M1/0631 ,  G06F17/10 ,  H03H17/06 ,  H03M1/0881 ,  H03M1/207 ,  H03M1/208

摘要： A signal processor and method of signal processing is disclosed. The signal processor includes a differentiator and an extrapolator coupled to the differentiator. The differentiator is configured to receive an input signal and to generate a vector. The input signal is band-limited. The vector includes at least one chromatic derivative. The extrapolator is coupled to the differentiator and is configured to generate an output signal.

摘要翻译： 公开了信号处理器和信号处理方法。 信号处理器包括耦合到微分器的微分器和外推器。 微分器被配置为接收输入信号并产生矢量。 输入信号是带限制的。 向量包括至少一个色差。 外推器被耦合到微分器并被配置为产生输出信号。