公开(公告)号：US06406953B1

公开(公告)日：2002-06-18

申请号：US09053557

申请日：1998-04-01

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

摘要翻译： 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAMS和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US06274509B1

公开(公告)日：2001-08-14

申请号：US09239457

申请日：1999-01-28

申请人： Tzung-Rue Hsieh ,  Wen-Wei Lo

发明人： Tzung-Rue Hsieh ,  Wen-Wei Lo

IPC分类号： H01L2131

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31612

摘要： A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material. The planarizing method of the invention has the advantage of not requiring a photolithography step required in a prior art planarization process. In addition, the planarization method of the invention has the advantage of not requiring a process step that subjects an integrated circuit to relatively high temperatures that can have adverse effects on metal conductors present therein.

摘要翻译： 本文公开了平面化电介质材料层的方法，其特别适用于平坦化层间电介质（ILD）或金属间电介质（IMD）。 平面化方法包括以下步骤：在电介质材料上沉积一层牺牲氧化物，在低于约500摄氏度的温度下通过溅射或等离子体增强化学气相沉积（PECVD）在牺牲氧化物层上沉积非晶硅层 ，对所述非晶硅层进行第一化学机械抛光以形成用于随后的蚀刻步骤的自对准掩模，蚀刻所述牺牲氧化物层的一部分以在其中形成通道，并执行第二化学机械抛光以除去 剩余的非晶硅层和剩余的牺牲氧化物，并且基本平坦化下面的介电材料。 本发明的平面化方法具有不需要现有技术的平坦化处理所需的光刻步骤的优点。 此外，本发明的平面化方法的优点在于不需要使集成电路处于对其中存在的金属导体具有不利影响的相对高的温度的处理步骤。

公开(公告)号：US6133597A

公开(公告)日：2000-10-17

申请号：US900560

申请日：1997-07-25

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

摘要翻译： 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAM和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与另一方面的相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US06777280B2

公开(公告)日：2004-08-17

申请号：US10136498

申请日：2002-04-30

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.