公开(公告)号：US08988108B2

公开(公告)日：2015-03-24

申请号：US13724218

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Quinnell ,  Christopher Thomas

IPC: H03K19/00 ,  H03K19/096 ,  G06F1/10 ,  G06F1/32

CPC classification number: H03K19/096 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

Abstract: Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a clock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

Abstract translation: 将时钟信号分配给集成电路的逻辑器件的方法。 该方法包括由逻辑元件控制由时钟同步器分配的时钟信号并将时钟信号分配给至少一个第一逻辑器件，其中逻辑元件允许第一时钟门控器分配时钟 只有当至少一个第一逻辑器件需要时钟信号时才会发出信号。 一种被配置为执行这种方法的集成电路。 这种集成电路的制造。

公开(公告)号：US20140176190A1

公开(公告)日：2014-06-26

申请号：US13724218

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Eric Quinnell ,  Christopher Thomas

IPC: H03K19/096

CPC classification number: H03K19/096 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

Abstract: Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a dock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

Abstract translation: 将时钟信号分配给集成电路的逻辑器件的方法。 该方法包括通过逻辑元件控制由码头门控器分配时钟信号并将时钟信号分配给至少一个第一逻辑器件，其中逻辑元件允许第一时钟门控器分配时钟 只有当至少一个第一逻辑器件需要时钟信号时才会发出信号。 一种被配置为执行这种方法的集成电路。 这种集成电路的制造。

公开(公告)号：US20140237312A1

公开(公告)日：2014-08-21

申请号：US13773501

申请日：2013-02-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Atchyuth K. Gorti ,  Aditya Jagirdar ,  Bikash Kumar Agarwal ,  Eric Quinnell

IPC: G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract translation: 报告集成电路设备的扫描预热方法。 一种这样的方法可以包括以等于测试时钟频率的扫描时钟第一频率将扫描测试激励加载并从集成电路器件的第一组逻辑元件卸载扫描测试响应; 通过扫描预热单元将扫描时钟从第一频率调整到第二频率，其中扫描时钟第二频率等于系统时钟频率; 并且以扫描时钟第二频率通过移位逻辑捕获扫描测试响应。 我们还会报告包含配置为实现该方法的组件以及这些处理器的制造的处理器。 这些方法及其实现可以减少在测试集成电路器件的逻辑元件时通常发生的di / dt事件。

公开(公告)号：US09291676B2

公开(公告)日：2016-03-22

申请号：US13773501

申请日：2013-02-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Atchyuth K Gorti ,  Aditya Jagirdar ,  Bikash Kumar Agarwal ,  Eric Quinnell

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract translation: 报告集成电路设备的扫描预热方法。 一种这样的方法可以包括以等于测试时钟频率的扫描时钟第一频率将扫描测试激励加载并从集成电路器件的第一组逻辑元件卸载扫描测试响应; 通过扫描预热单元将扫描时钟从第一频率调整到第二频率，其中扫描时钟第二频率等于系统时钟频率; 并且以扫描时钟第二频率通过移位逻辑捕获扫描测试响应。 我们还会报告包含配置为实现该方法的组件以及这些处理器的制造的处理器。 这些方法及其实现可以减少在测试集成电路器件的逻辑元件时通常发生的di / dt事件。