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    SUPERCONDUCTOR GROUND PLANE PATTERNING GEOMETRIES THAT ATTRACT MAGNETIC FLUX
    3.
    发明申请
    SUPERCONDUCTOR GROUND PLANE PATTERNING GEOMETRIES THAT ATTRACT MAGNETIC FLUX 审中-公开

    公开(公告)号：US20200287118A1

    公开(公告)日：2020-09-10

    申请号：US16296007

    申请日：2019-03-07

    申请人： ANNA Y. HERR ,  VLADIMIR V. TALANOV ,  QUENTIN P. HERR

    发明人： ANNA Y. HERR ,  VLADIMIR V. TALANOV ,  QUENTIN P. HERR

    IPC分类号： H01L39/14 ,  H01L39/24 ,  H01L39/08

    摘要： Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

    PHASE HYSTERETIC MAGNETIC JOSEPHSON JUNCTION MEMORY CELL
    4.
    发明申请
    PHASE HYSTERETIC MAGNETIC JOSEPHSON JUNCTION MEMORY CELL 审中-公开
    相位滞后磁性JOSEPHSON连接存储单元

    公开(公告)号：US20160267964A1

    公开(公告)日：2016-09-15

    申请号：US15013687

    申请日：2016-02-02

    申请人： ANNA Y. HERR ,  QUENTIN P. HERR ,  ANDREW HOSTETLER MIKLICH

    发明人： ANNA Y. HERR ,  QUENTIN P. HERR ,  ANDREW HOSTETLER MIKLICH

    IPC分类号： G11C11/44

    CPC分类号： G11C11/44 ,  G11C11/16

    摘要： One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.

    摘要翻译： 一个实施例描述了一个存储单元。 存储器单元包括相滞后磁约瑟夫逊结（PHMJJ），其被配置为存储对应于二进制逻辑1状态的第一二进制逻辑状态和对应于二进制逻辑0状态的第二二进制逻辑状态之一，以响应于 写入电流，其被提供给存储器单元并且基于所存储的数字状态生成超导相位。 存储器单元还包括超导读取选择器件，其被配置为响应于提供给存储器单元的读取电流来实现读取操作。 存储单元还包括至少一个约瑟夫逊结，其被配置为在读取操作期间基于PHMJJ的超导相位提供输出，对应于所存储的数字状态的输出。

    CLOCK DISTRIBUTION SYSTEM
    5.
    发明申请
    CLOCK DISTRIBUTION SYSTEM 审中-公开
    时钟分配系统

    公开(公告)号：US20160370822A1

    公开(公告)日：2016-12-22

    申请号：US14746377

    申请日：2015-06-22

    申请人： JOSHUA A. STRONG ,  ANNA Y. HERR ,  QUENTIN P. HERR ,  STEVEN B. SHAUCK

    发明人： JOSHUA A. STRONG ,  ANNA Y. HERR ,  QUENTIN P. HERR ,  STEVEN B. SHAUCK

    IPC分类号： G06F1/10

    摘要： One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.

    摘要翻译： 一个实施例包括时钟分配系统。 该系统包括被配置为接收和谐振正弦时钟信号的驻波谐振器。 驻波共振器包括与正弦时钟信号的峰值电流幅度相关联的至少一个反节点部分。 该系统还包括互连至少一个反节点部分和相关电路中的每一个的至少一个时钟线。 至少一个时钟线可被配置为传播用于与相关电路相关联的定时功能的正弦时钟信号。

    SUPERCONDUCTING CIRCUIT PHYSICAL LAYOUT SYSTEM AND METHOD
    6.
    发明申请
    SUPERCONDUCTING CIRCUIT PHYSICAL LAYOUT SYSTEM AND METHOD 有权
    超导电路物理布置系统及方法

    公开(公告)号：US20160034609A1

    公开(公告)日：2016-02-04

    申请号：US14449524

    申请日：2014-08-01

    申请人： ANNA Y. HERR ,  Quentin P. Herr

    发明人： ANNA Y. HERR ,  Quentin P. Herr

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/08 ,  G06N99/002

    摘要： Systems and methods are provided for physical layout of superconductor circuits. The physical layout system and method is configured to place and route the superconducting circuits by first placing the gates in the form of gate tiles within unoccupied areas of a predetermined circuit design based on a netlist. Each gate tile type includes a particular gate type and a plurality of unassigned Josephson junctions that can be employed in the gates and/or the active interconnects. Inductive wires are then routed between gates incorporating and assigning the Josephson junctions to produce active interconnects between the I/O terminals of the gates based on connections defined in the netlist.

    摘要翻译： 提供了用于超导体电路的物理布局的系统和方法。 物理布局系统和方法被配置为通过首先将门板形式的门以基于网表的预定电路设计的未占用区域的形式放置和布线。 每个栅极瓦片类型包括可以在栅极和/或有源互连中使用的特定栅极类型和多个未分配的约瑟夫逊结。 感应电线然后在并入并分配约瑟夫逊结的门之间布线，以根据网表中定义的连接在门的I / O端之间产生有源互连。

    SUPERCONDUCTIVE GATE SYSTEM
    7.
    发明申请
    SUPERCONDUCTIVE GATE SYSTEM 有权
    超级门系统

    公开(公告)号：US20160013791A1

    公开(公告)日：2016-01-14

    申请号：US14325518

    申请日：2014-07-08

    申请人： ANNA Y. HERR ,  QUENTIN P. HERR

    发明人： ANNA Y. HERR ,  QUENTIN P. HERR

    IPC分类号： H03K19/00 ,  H03K19/195

    CPC分类号： H03K19/0008 ,  B82Y10/00 ,  G06N99/002 ,  G11C11/44 ,  H03K3/38 ,  H03K19/1952

    摘要： One embodiment includes a superconductive gate system. The superconductive gate system includes a Josephson D-gate circuit comprising a bi-stable loop configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum (SFQ) pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input. The digital state can be provided at an output. The readout circuit is coupled to the output and can be configured to reproduce the digital state as an output signal.

    摘要翻译： 一个实施例包括超导门系统。 超导栅极系统包括约瑟夫森D门电路，其包括双稳态环路，其被配置为响应于在第一数据状态和第二数据状态上提供的使能单通量量子（SFQ）脉冲而将数字状态存储为第一数据状态和第二数据状态之一 启用输入和相应的存在或不存在在数据输入上提供的数据SFQ脉冲。 数字状态可以在输出端提供。 读出电路耦合到输出，并且可以被配置为将数字状态再现为输出信号。

    JOSEPHSON MAGNETIC MEMORY CELL SYSTEM
    8.
    发明申请
    JOSEPHSON MAGNETIC MEMORY CELL SYSTEM 有权
    JOSEPHSON磁记忆体系统

    公开(公告)号：US20150043273A1

    公开(公告)日：2015-02-12

    申请号：US13485397

    申请日：2012-05-31

    申请人： OFER NAAMAN ,  DONALD L. MILLER ,  ANNA Y. HERR ,  NORMAN O. BIRGE

    发明人： OFER NAAMAN ,  DONALD L. MILLER ,  ANNA Y. HERR ,  NORMAN O. BIRGE

    IPC分类号： G11C11/44 ,  G11C11/16

    CPC分类号： G11C11/44 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L39/223 ,  H01L43/08

    摘要： One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.

    摘要翻译： 本发明的一个方面包括约瑟夫森磁存储系统。 该系统包括传导读取电流的超导电极。 该系统还包括滞后磁性约瑟夫逊结（HMJJ）。 HMJJ可以存储二进制值，并将与流过HMJJ的读取电流相关联的超导对从单态状态转换为三态态。 该系统还包括磁耦合到HMJJ并被配置为响应于至少一个写入电流将二进制值写入到HMJJ中的写入电路和配置成响应于应用中确定存储在HMJJ中的二进制值的读取电路 读取电流到HMJJ。