公开(公告)号：US09383806B2

公开(公告)日：2016-07-05

申请号：US13864723

申请日：2013-04-17

Applicant: Apple Inc.

Inventor： Wei-Han Lien ,  Gerard R Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。

公开(公告)号：US09411404B2

公开(公告)日：2016-08-09

申请号：US14157171

申请日：2014-01-16

Applicant: Apple Inc.

Inventor： Rohit Kumar ,  Suresh Periyacheri

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3243 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/22

Abstract: An apparatus is disclosed for managing operational modes of a processor. The apparatus may include the processor which may include a coprocessor, an instruction queue, and a monitoring circuit for detecting instructions for the coprocessor in the instruction queue. The monitoring circuit may detect when the instruction queue holds no instructions for the coprocessor. If the instruction queue holds no instructions for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor consumes less power. The monitoring circuit may detect an instruction for the coprocessor in the instruction queue. In response to the instruction for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor may execute the instruction.

Abstract translation: 公开了一种用于管理处理器的操作模式的装置。 该装置可以包括可以包括协处理器，指令队列和用于检测指令队列中的协处理器的指令的监视电路的处理器。 监视电路可以检测指令队列何时不保存协处理器的指令。 如果指令队列不保存协处理器的指令，协处理器可以被置于协处理器消耗更少功率的模式中。 监视电路可以检测指令队列中协处理器的指令。 响应于协处理器的指令，协处理器可以被置于协处理器可以执行指令的模式中。

公开(公告)号：US20150033045A1

公开(公告)日：2015-01-29

申请号：US13948843

申请日：2013-07-23

Applicant: Apple Inc.

Inventor： Pankaj Raghuvanshi ,  Rohit Kumar ,  Suresh Periyacheri

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/4893 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: An apparatus for performing instruction throttling for a computing system is disclosed. The apparatus may include a first counter, a second counter, and a control circuit. The second counter may be configured to increment in response to a determination that a processing cycle of a processor has completed. The control circuit may be configured to initialize the first and second counters, detect the processor has issued and instruction, decrement the first counter in response to the detection of the issued instruction, block the processor from issuing instructions dependent upon the a value of the first counter, reset the first counter dependent upon a value of the second counter, and reset the second counter in response to a determination that the value of the second counter is greater than a pre-determined value.

Abstract translation: 公开了一种用于对计算系统执行指令调节的装置。 该装置可以包括第一计数器，第二计数器和控制电路。 第二计数器可以被配置为响应于处理器的处理周期的确定已经完成而递增。 控制电路可以被配置为初始化第一和第二计数器，检测处理器已经发出和指令，响应于所发出的指令的检测而减小第一计数器，阻止处理器发出指令，取决于第一和第二计数器的值 计数器，根据第二计数器的值复位第一计数器，并且响应于第二计数器的值大于预定值的确定而复位第二计数器。

公开(公告)号：US20150198992A1

公开(公告)日：2015-07-16

申请号：US14157171

申请日：2014-01-16

Applicant: Apple Inc.

Inventor： Rohit Kumar ,  Suresh Periyacheri

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/22

Abstract: An apparatus is disclosed for managing operational modes of a processor. The apparatus may include the processor which may include a coprocessor, an instruction queue, and a monitoring circuit for detecting instructions for the coprocessor in the instruction queue. The monitoring circuit may detect when the instruction queue holds no instructions for the coprocessor. If the instruction queue holds no instructions for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor consumes less power. The monitoring circuit may detect an instruction for the coprocessor in the instruction queue. In response to the instruction for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor may execute the instruction.

Abstract translation: 公开了一种用于管理处理器的操作模式的装置。 该装置可以包括可以包括协处理器，指令队列和用于检测指令队列中的协处理器的指令的监视电路的处理器。 监视电路可以检测指令队列何时不保存协处理器的指令。 如果指令队列不保存协处理器的指令，协处理器可以被置于协处理器消耗更少功率的模式中。 监视电路可以检测指令队列中协处理器的指令。 响应于协处理器的指令，协处理器可以被置于协处理器可以执行指令的模式中。

公开(公告)号：US20140317425A1

公开(公告)日：2014-10-23

申请号：US13864723

申请日：2013-04-17

Applicant: APPLE INC.

Inventor： Wei-Han Lien ,  Gerard R. Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R. Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。