公开(公告)号：US20140340122A1

公开(公告)日：2014-11-20

申请号：US13895624

申请日：2013-05-16

Applicant: ARM LIMITED

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

IPC: H02M3/156 ,  G01R19/00

CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

公开(公告)号：US20160118882A1

公开(公告)日：2016-04-28

申请号：US14922783

申请日：2015-10-26

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

IPC: H02M3/157 ,  G01R19/00

CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

公开(公告)号：US20180212582A1

公开(公告)日：2018-07-26

申请号：US15410922

申请日：2017-01-20

Applicant: ARM Limited

Inventor： Bal S. SANDHU ,  Mudit BHARGAVA ,  Akshay KUMAR ,  Piyush AGARWAL ,  Shidhartha DAS

IPC: H03H7/065

CPC classification number: H03H7/065 ,  H01L27/10 ,  H01L45/04 ,  H03H7/0153 ,  H03H7/06

Abstract: Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analogue or digital and work across a range of frequencies. Present techniques provide an electronic filter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device.

公开(公告)号：US20180175615A1

公开(公告)日：2018-06-21

申请号：US15381393

申请日：2016-12-16

Applicant: ARM Limited

Inventor： Bal S. SANDHU ,  Lucian SHIFREN ,  Glen Arnold ROSENDALE

IPC: H02H9/04 ,  H03K5/08 ,  H01L23/64

Abstract: A circuit is provided for limiting an applied voltage applied between a power line and an electrical ground. The circuit includes a transistive element connected between the power line and the electrical ground to provide a channel, where current flow through the channel is controlled by a control voltage provided to a control terminal of the transistive element. A first Correlated Electron Material (CEM) device having an impedance state is coupled between the power line and a first node, and a sensing circuit coupled between the first node and the control terminal of the transistive element. The sensing circuit is configured to detect a voltage drop across the CEM device and to provide the control voltage. The channel of the transistive element is opened when the detected voltage drop across the CEM device exceeds a threshold. The CEM device may contain a transition metal oxide (TMO), for example.